About the Execution of LoLA for RefineWMG-PT-100101
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16197.084 | 399857.00 | 404452.00 | 1539.80 | ????????T??????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662341200762.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RefineWMG-PT-100101, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662341200762
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 716K
-rw-r--r-- 1 mcc users 7.7K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 85K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K May 19 07:14 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 19 16:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 23 07:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 13 04:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 113K Apr 13 04:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 13 04:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 110K Apr 13 04:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:47 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:47 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 7 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 218K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-00
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-01
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-02
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-03
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-04
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-05
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-06
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-07
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-08
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-09
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-10
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2024-11
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2023-12
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2023-13
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2023-14
FORMULA_NAME RefineWMG-PT-100101-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717354515171
FORMULA RefineWMG-PT-100101-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717354915028
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 24 RefineWMG-PT-100101-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type FNDP) for 24 RefineWMG-PT-100101-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 24 RefineWMG-PT-100101-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for RefineWMG-PT-100101-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 56 (type FNDP) for RefineWMG-PT-100101-CTLFireability-2024-08 (obsolete)
[[35mlola[0m][W] CANCELED task # 57 (type EQUN) for RefineWMG-PT-100101-CTLFireability-2024-08 (obsolete)
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 RefineWMG-PT-100101-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 33 RefineWMG-PT-100101-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 33 RefineWMG-PT-100101-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for RefineWMG-PT-100101-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for RefineWMG-PT-100101-CTLFireability-2024-11
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for RefineWMG-PT-100101-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 56 (type FNDP) for RefineWMG-PT-100101-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 CTL EXCL 5/211 8/2000 RefineWMG-PT-100101-CTLFireability-2024-07 1894559 m, 378911 m/sec, 12356477 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 CTL EXCL 10/211 15/2000 RefineWMG-PT-100101-CTLFireability-2024-07 3579596 m, 337007 m/sec, 25218786 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for RefineWMG-PT-100101-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4763196
[[35mlola[0m][I] fired transitions : 34635989
[[35mlola[0m][I] time used : 14
[[35mlola[0m][I] memory pages used : 20
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 RefineWMG-PT-100101-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for RefineWMG-PT-100101-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 607
[[35mlola[0m][I] fired transitions : 808
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 RefineWMG-PT-100101-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 1/239 2/2000 RefineWMG-PT-100101-CTLFireability-2023-14 99324 m, 19864 m/sec, 440960 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 6/239 8/2000 RefineWMG-PT-100101-CTLFireability-2023-14 645477 m, 109230 m/sec, 2359369 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 11/239 16/2000 RefineWMG-PT-100101-CTLFireability-2023-14 1254918 m, 121888 m/sec, 4332910 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 16/239 22/2000 RefineWMG-PT-100101-CTLFireability-2023-14 1802014 m, 109419 m/sec, 6241942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 21/239 29/2000 RefineWMG-PT-100101-CTLFireability-2023-14 2352947 m, 110186 m/sec, 8176249 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 26/239 36/2000 RefineWMG-PT-100101-CTLFireability-2023-14 2934036 m, 116217 m/sec, 10126901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 31/239 43/2000 RefineWMG-PT-100101-CTLFireability-2023-14 3487258 m, 110644 m/sec, 12036445 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 36/239 49/2000 RefineWMG-PT-100101-CTLFireability-2023-14 4027979 m, 108144 m/sec, 13898340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 41/239 56/2000 RefineWMG-PT-100101-CTLFireability-2023-14 4604218 m, 115247 m/sec, 15807031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 46/239 63/2000 RefineWMG-PT-100101-CTLFireability-2023-14 5111914 m, 101539 m/sec, 17634328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 51/239 69/2000 RefineWMG-PT-100101-CTLFireability-2023-14 5654902 m, 108597 m/sec, 19512389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 56/239 76/2000 RefineWMG-PT-100101-CTLFireability-2023-14 6259911 m, 121001 m/sec, 21472244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 61/239 83/2000 RefineWMG-PT-100101-CTLFireability-2023-14 6815937 m, 111205 m/sec, 23360058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 66/239 89/2000 RefineWMG-PT-100101-CTLFireability-2023-14 7325606 m, 101933 m/sec, 25221875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 71/239 96/2000 RefineWMG-PT-100101-CTLFireability-2023-14 7911578 m, 117194 m/sec, 27122456 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 76/239 103/2000 RefineWMG-PT-100101-CTLFireability-2023-14 8462103 m, 110105 m/sec, 28995121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 81/239 109/2000 RefineWMG-PT-100101-CTLFireability-2023-14 8981712 m, 103921 m/sec, 30825692 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 86/239 116/2000 RefineWMG-PT-100101-CTLFireability-2023-14 9520367 m, 107731 m/sec, 32659654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 91/239 122/2000 RefineWMG-PT-100101-CTLFireability-2023-14 10063930 m, 108712 m/sec, 34572393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 96/239 129/2000 RefineWMG-PT-100101-CTLFireability-2023-14 10670964 m, 121406 m/sec, 36538436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 101/239 136/2000 RefineWMG-PT-100101-CTLFireability-2023-14 11185132 m, 102833 m/sec, 38376538 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 106/239 142/2000 RefineWMG-PT-100101-CTLFireability-2023-14 11708590 m, 104691 m/sec, 40215428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 111/239 149/2000 RefineWMG-PT-100101-CTLFireability-2023-14 12274839 m, 113249 m/sec, 42139924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 116/239 155/2000 RefineWMG-PT-100101-CTLFireability-2023-14 12840448 m, 113121 m/sec, 44056437 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 121/239 163/2000 RefineWMG-PT-100101-CTLFireability-2023-14 13446320 m, 121174 m/sec, 45999146 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 126/239 169/2000 RefineWMG-PT-100101-CTLFireability-2023-14 13960383 m, 102812 m/sec, 47841926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 131/239 175/2000 RefineWMG-PT-100101-CTLFireability-2023-14 14443126 m, 96548 m/sec, 49653534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 136/239 182/2000 RefineWMG-PT-100101-CTLFireability-2023-14 15015104 m, 114395 m/sec, 51536314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 141/239 188/2000 RefineWMG-PT-100101-CTLFireability-2023-14 15559335 m, 108846 m/sec, 53371921 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 146/239 194/2000 RefineWMG-PT-100101-CTLFireability-2023-14 16087643 m, 105661 m/sec, 55252401 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 151/239 201/2000 RefineWMG-PT-100101-CTLFireability-2023-14 16637224 m, 109916 m/sec, 57143973 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 156/239 207/2000 RefineWMG-PT-100101-CTLFireability-2023-14 17163221 m, 105199 m/sec, 58994175 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 161/239 214/2000 RefineWMG-PT-100101-CTLFireability-2023-14 17750441 m, 117444 m/sec, 60909422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 166/239 220/2000 RefineWMG-PT-100101-CTLFireability-2023-14 18247607 m, 99433 m/sec, 62703918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 171/239 227/2000 RefineWMG-PT-100101-CTLFireability-2023-14 18789456 m, 108369 m/sec, 64589086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 176/239 234/2000 RefineWMG-PT-100101-CTLFireability-2023-14 19404717 m, 123052 m/sec, 66560675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 181/239 241/2000 RefineWMG-PT-100101-CTLFireability-2023-14 19951698 m, 109396 m/sec, 68403843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 186/239 247/2000 RefineWMG-PT-100101-CTLFireability-2023-14 20427005 m, 95061 m/sec, 70198584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 191/239 254/2000 RefineWMG-PT-100101-CTLFireability-2023-14 21009500 m, 116499 m/sec, 72130159 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 196/239 260/2000 RefineWMG-PT-100101-CTLFireability-2023-14 21531602 m, 104420 m/sec, 73973282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 201/239 266/2000 RefineWMG-PT-100101-CTLFireability-2023-14 22088439 m, 111367 m/sec, 75842394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 206/239 273/2000 RefineWMG-PT-100101-CTLFireability-2023-14 22626977 m, 107707 m/sec, 77696232 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 211/239 279/2000 RefineWMG-PT-100101-CTLFireability-2023-14 23131908 m, 100986 m/sec, 79517964 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 279
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 216/239 286/2000 RefineWMG-PT-100101-CTLFireability-2023-14 23711732 m, 115964 m/sec, 81409678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 286
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 221/239 293/2000 RefineWMG-PT-100101-CTLFireability-2023-14 24283529 m, 114359 m/sec, 83325634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 226/239 300/2000 RefineWMG-PT-100101-CTLFireability-2023-14 24843190 m, 111932 m/sec, 85224267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 231/239 306/2000 RefineWMG-PT-100101-CTLFireability-2023-14 25382025 m, 107767 m/sec, 87070314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 306
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 236/239 313/2000 RefineWMG-PT-100101-CTLFireability-2023-14 25889390 m, 101473 m/sec, 88934280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 51 (type EXCL) for RefineWMG-PT-100101-CTLFireability-2023-14 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 320
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 39 RefineWMG-PT-100101-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 238 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 RefineWMG-PT-100101-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 3345 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for RefineWMG-PT-100101-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 101
[[35mlola[0m][I] fired transitions : 302
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 51 (type EXCL) for RefineWMG-PT-100101-CTLFireability-2023-14 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-13: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 325
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 39 RefineWMG-PT-100101-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for RefineWMG-PT-100101-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 102
[[35mlola[0m][I] fired transitions : 101
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 39 RefineWMG-PT-100101-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 278 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for RefineWMG-PT-100101-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 RefineWMG-PT-100101-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 303 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 5/303 6/2000 RefineWMG-PT-100101-CTLFireability-2023-12 384106 m, 76821 m/sec, 577985 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 10/303 11/2000 RefineWMG-PT-100101-CTLFireability-2023-12 764685 m, 76115 m/sec, 1150699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 15/303 16/2000 RefineWMG-PT-100101-CTLFireability-2023-12 1147261 m, 76515 m/sec, 1726486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 20/303 21/2000 RefineWMG-PT-100101-CTLFireability-2023-12 1521455 m, 74838 m/sec, 2289653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 341
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 25/303 26/2000 RefineWMG-PT-100101-CTLFireability-2023-12 1896728 m, 75054 m/sec, 2854417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 346
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 30/303 30/2000 RefineWMG-PT-100101-CTLFireability-2023-12 2270118 m, 74678 m/sec, 3416395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 350
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 35/303 35/2000 RefineWMG-PT-100101-CTLFireability-2023-12 2646181 m, 75212 m/sec, 3982280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 40/303 40/2000 RefineWMG-PT-100101-CTLFireability-2023-12 3017323 m, 74228 m/sec, 4540854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 360
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 45/303 45/2000 RefineWMG-PT-100101-CTLFireability-2023-12 3386463 m, 73828 m/sec, 5096348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 365
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 50/303 50/2000 RefineWMG-PT-100101-CTLFireability-2023-12 3754090 m, 73525 m/sec, 5649604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 370
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 55/303 55/2000 RefineWMG-PT-100101-CTLFireability-2023-12 4118201 m, 72822 m/sec, 6197633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 375
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 60/303 60/2000 RefineWMG-PT-100101-CTLFireability-2023-12 4483078 m, 72975 m/sec, 6746739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 65/303 65/2000 RefineWMG-PT-100101-CTLFireability-2023-12 4852894 m, 73963 m/sec, 7303281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 385
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 70/303 70/2000 RefineWMG-PT-100101-CTLFireability-2023-12 5220991 m, 73619 m/sec, 7857262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 390
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 75/303 75/2000 RefineWMG-PT-100101-CTLFireability-2023-12 5594642 m, 74730 m/sec, 8419569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 395
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 80/303 80/2000 RefineWMG-PT-100101-CTLFireability-2023-12 5962553 m, 73582 m/sec, 8973248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 400
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 85/303 85/2000 RefineWMG-PT-100101-CTLFireability-2023-12 6325990 m, 72687 m/sec, 9520265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 405
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 90/303 90/2000 RefineWMG-PT-100101-CTLFireability-2023-12 6698918 m, 74585 m/sec, 10081494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 410
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 95/303 95/2000 RefineWMG-PT-100101-CTLFireability-2023-12 7069160 m, 74048 m/sec, 10638643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 415
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 100/303 99/2000 RefineWMG-PT-100101-CTLFireability-2023-12 7440074 m, 74182 m/sec, 11196834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 419
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 105/303 104/2000 RefineWMG-PT-100101-CTLFireability-2023-12 7804639 m, 72913 m/sec, 11745542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 424
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 110/303 109/2000 RefineWMG-PT-100101-CTLFireability-2023-12 8167817 m, 72635 m/sec, 12292051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 429
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 115/303 114/2000 RefineWMG-PT-100101-CTLFireability-2023-12 8524174 m, 71271 m/sec, 12828396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 434
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 120/303 119/2000 RefineWMG-PT-100101-CTLFireability-2023-12 8889704 m, 73106 m/sec, 13378517 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 439
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 125/303 124/2000 RefineWMG-PT-100101-CTLFireability-2023-12 9257774 m, 73614 m/sec, 13932412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 444
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 130/303 129/2000 RefineWMG-PT-100101-CTLFireability-2023-12 9620220 m, 72489 m/sec, 14477861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 449
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2024-08: EF true state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100101-CTLFireability-2023-13: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100101-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2024-11: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100101-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 135/303 133/2000 RefineWMG-PT-100101-CTLFireability-2023-12 9981499 m, 72255 m/sec, 15021579 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 402 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-100101"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RefineWMG-PT-100101, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662341200762"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-100101.tgz
mv RefineWMG-PT-100101 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;