About the Execution of LoLA for RefineWMG-PT-100100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16199.596 | 468080.00 | 472382.00 | 1521.10 | ??T????????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662341200754.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RefineWMG-PT-100100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662341200754
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 620K
-rw-r--r-- 1 mcc users 6.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 23 07:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 23 07:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.2K Apr 13 04:59 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 80K Apr 13 04:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.7K Apr 13 04:58 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 65K Apr 13 04:58 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:47 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:47 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 7 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 218K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-00
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-01
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-02
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-03
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-04
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-05
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-06
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-07
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-08
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-09
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-10
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2024-11
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2023-12
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2023-13
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2023-14
FORMULA_NAME RefineWMG-PT-100100-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717354431242
FORMULA RefineWMG-PT-100100-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717354899322
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 55 (type EQUN) for 6 RefineWMG-PT-100100-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 6 RefineWMG-PT-100100-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for RefineWMG-PT-100100-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 55 (type EQUN) for RefineWMG-PT-100100-CTLFireability-2024-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 55 (type EQUN) for RefineWMG-PT-100100-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 RefineWMG-PT-100100-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 12 RefineWMG-PT-100100-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 12 RefineWMG-PT-100100-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for RefineWMG-PT-100100-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for RefineWMG-PT-100100-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for RefineWMG-PT-100100-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 36781
[[35mlola[0m][I] fired transitions : 72052
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 RefineWMG-PT-100100-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for RefineWMG-PT-100100-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 10302
[[35mlola[0m][I] fired transitions : 10402
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 RefineWMG-PT-100100-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for RefineWMG-PT-100100-CTLFireability-2023-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12214
[[35mlola[0m][I] fired transitions : 23674
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 RefineWMG-PT-100100-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 4/276 6/2000 RefineWMG-PT-100100-CTLFireability-2024-11 622002 m, 124400 m/sec, 1857286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 9/276 13/2000 RefineWMG-PT-100100-CTLFireability-2024-11 1349561 m, 145511 m/sec, 4033477 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 14/276 20/2000 RefineWMG-PT-100100-CTLFireability-2024-11 2086594 m, 147406 m/sec, 6238026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 19/276 27/2000 RefineWMG-PT-100100-CTLFireability-2024-11 2806509 m, 143983 m/sec, 8391464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 24/276 34/2000 RefineWMG-PT-100100-CTLFireability-2024-11 3532872 m, 145272 m/sec, 10564145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 29/276 40/2000 RefineWMG-PT-100100-CTLFireability-2024-11 4251814 m, 143788 m/sec, 12714555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 34/276 47/2000 RefineWMG-PT-100100-CTLFireability-2024-11 4967711 m, 143179 m/sec, 14855980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 39/276 54/2000 RefineWMG-PT-100100-CTLFireability-2024-11 5685770 m, 143611 m/sec, 17003805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 44/276 60/2000 RefineWMG-PT-100100-CTLFireability-2024-11 6411177 m, 145081 m/sec, 19173595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 49/276 67/2000 RefineWMG-PT-100100-CTLFireability-2024-11 7123590 m, 142482 m/sec, 21304590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 54/276 74/2000 RefineWMG-PT-100100-CTLFireability-2024-11 7846510 m, 144584 m/sec, 23466954 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 59/276 81/2000 RefineWMG-PT-100100-CTLFireability-2024-11 8560335 m, 142765 m/sec, 25602121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 64/276 87/2000 RefineWMG-PT-100100-CTLFireability-2024-11 9274414 m, 142815 m/sec, 27738068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 69/276 94/2000 RefineWMG-PT-100100-CTLFireability-2024-11 9996047 m, 144326 m/sec, 29896550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 74/276 101/2000 RefineWMG-PT-100100-CTLFireability-2024-11 10703263 m, 141443 m/sec, 32011964 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 79/276 107/2000 RefineWMG-PT-100100-CTLFireability-2024-11 11405684 m, 140484 m/sec, 34113013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 84/276 114/2000 RefineWMG-PT-100100-CTLFireability-2024-11 12109519 m, 140767 m/sec, 36218269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 89/276 120/2000 RefineWMG-PT-100100-CTLFireability-2024-11 12826937 m, 143483 m/sec, 38364261 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 94/276 127/2000 RefineWMG-PT-100100-CTLFireability-2024-11 13552892 m, 145191 m/sec, 40535693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 99/276 134/2000 RefineWMG-PT-100100-CTLFireability-2024-11 14258439 m, 141109 m/sec, 42646087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 104/276 141/2000 RefineWMG-PT-100100-CTLFireability-2024-11 14980853 m, 144482 m/sec, 44806989 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 109/276 147/2000 RefineWMG-PT-100100-CTLFireability-2024-11 15703301 m, 144489 m/sec, 46967909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 114/276 154/2000 RefineWMG-PT-100100-CTLFireability-2024-11 16422114 m, 143762 m/sec, 49118009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 119/276 161/2000 RefineWMG-PT-100100-CTLFireability-2024-11 17155155 m, 146608 m/sec, 51310684 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 124/276 168/2000 RefineWMG-PT-100100-CTLFireability-2024-11 17876391 m, 144247 m/sec, 53467979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 129/276 174/2000 RefineWMG-PT-100100-CTLFireability-2024-11 18600921 m, 144906 m/sec, 55635206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 134/276 181/2000 RefineWMG-PT-100100-CTLFireability-2024-11 19335750 m, 146965 m/sec, 57833173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 139/276 188/2000 RefineWMG-PT-100100-CTLFireability-2024-11 20059165 m, 144683 m/sec, 59997012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 144/276 195/2000 RefineWMG-PT-100100-CTLFireability-2024-11 20779494 m, 144065 m/sec, 62151708 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 149/276 202/2000 RefineWMG-PT-100100-CTLFireability-2024-11 21498395 m, 143780 m/sec, 64301997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 154/276 208/2000 RefineWMG-PT-100100-CTLFireability-2024-11 22208009 m, 141922 m/sec, 66424601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 159/276 215/2000 RefineWMG-PT-100100-CTLFireability-2024-11 22933147 m, 145027 m/sec, 68593617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 164/276 222/2000 RefineWMG-PT-100100-CTLFireability-2024-11 23649063 m, 143183 m/sec, 70734991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 169/276 228/2000 RefineWMG-PT-100100-CTLFireability-2024-11 24364854 m, 143158 m/sec, 72876101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 174/276 235/2000 RefineWMG-PT-100100-CTLFireability-2024-11 25098846 m, 146798 m/sec, 75071564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 179/276 242/2000 RefineWMG-PT-100100-CTLFireability-2024-11 25819012 m, 144033 m/sec, 77225719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 184/276 249/2000 RefineWMG-PT-100100-CTLFireability-2024-11 26548689 m, 145935 m/sec, 79408315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 189/276 256/2000 RefineWMG-PT-100100-CTLFireability-2024-11 27279658 m, 146193 m/sec, 81594765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 194/276 262/2000 RefineWMG-PT-100100-CTLFireability-2024-11 27992082 m, 142484 m/sec, 83725759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 199/276 269/2000 RefineWMG-PT-100100-CTLFireability-2024-11 28718880 m, 145359 m/sec, 85899738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 204/276 276/2000 RefineWMG-PT-100100-CTLFireability-2024-11 29445496 m, 145323 m/sec, 88073115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 276
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 209/276 283/2000 RefineWMG-PT-100100-CTLFireability-2024-11 30155431 m, 141987 m/sec, 90196707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 214/276 289/2000 RefineWMG-PT-100100-CTLFireability-2024-11 30883215 m, 145556 m/sec, 92373604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 289
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 219/276 296/2000 RefineWMG-PT-100100-CTLFireability-2024-11 31597642 m, 142885 m/sec, 94510544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 224/276 303/2000 RefineWMG-PT-100100-CTLFireability-2024-11 32311702 m, 142812 m/sec, 96646452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 303
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 229/276 310/2000 RefineWMG-PT-100100-CTLFireability-2024-11 33042315 m, 146122 m/sec, 98831860 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 310
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 234/276 316/2000 RefineWMG-PT-100100-CTLFireability-2024-11 33780720 m, 147681 m/sec, 101040531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 316
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 239/276 323/2000 RefineWMG-PT-100100-CTLFireability-2024-11 34515102 m, 146876 m/sec, 103237241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 323
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 244/276 330/2000 RefineWMG-PT-100100-CTLFireability-2024-11 35255463 m, 148072 m/sec, 105451709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 330
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 249/276 337/2000 RefineWMG-PT-100100-CTLFireability-2024-11 35984729 m, 145853 m/sec, 107633112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 337
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 254/276 344/2000 RefineWMG-PT-100100-CTLFireability-2024-11 36716426 m, 146339 m/sec, 109821723 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 344
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 259/276 351/2000 RefineWMG-PT-100100-CTLFireability-2024-11 37448970 m, 146508 m/sec, 112012883 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 264/276 358/2000 RefineWMG-PT-100100-CTLFireability-2024-11 38181902 m, 146586 m/sec, 114205237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 358
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 269/276 364/2000 RefineWMG-PT-100100-CTLFireability-2024-11 38912168 m, 146053 m/sec, 116389563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 364
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 274/276 371/2000 RefineWMG-PT-100100-CTLFireability-2024-11 39644838 m, 146534 m/sec, 118581101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 38 (type EXCL) for RefineWMG-PT-100100-CTLFireability-2024-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 RefineWMG-PT-100100-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 RefineWMG-PT-100100-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 3320 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for RefineWMG-PT-100100-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5254
[[35mlola[0m][I] fired transitions : 10402
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 38 (type EXCL) for RefineWMG-PT-100100-CTLFireability-2024-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 RefineWMG-PT-100100-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 301 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for RefineWMG-PT-100100-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 10504
[[35mlola[0m][I] fired transitions : 10706
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 RefineWMG-PT-100100-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 331 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for RefineWMG-PT-100100-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 608
[[35mlola[0m][I] fired transitions : 708
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 RefineWMG-PT-100100-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 368 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for RefineWMG-PT-100100-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 24637
[[35mlola[0m][I] fired transitions : 48319
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 RefineWMG-PT-100100-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 414 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 5/414 5/2000 RefineWMG-PT-100100-CTLFireability-2024-05 343462 m, 68692 m/sec, 860302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 10/414 9/2000 RefineWMG-PT-100100-CTLFireability-2024-05 665266 m, 64360 m/sec, 1666374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 15/414 14/2000 RefineWMG-PT-100100-CTLFireability-2024-05 982501 m, 63447 m/sec, 2461088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 20/414 18/2000 RefineWMG-PT-100100-CTLFireability-2024-05 1297215 m, 62942 m/sec, 3249416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 25/414 22/2000 RefineWMG-PT-100100-CTLFireability-2024-05 1610302 m, 62617 m/sec, 4033742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 30/414 26/2000 RefineWMG-PT-100100-CTLFireability-2024-05 1923206 m, 62580 m/sec, 4817570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 35/414 30/2000 RefineWMG-PT-100100-CTLFireability-2024-05 2233801 m, 62119 m/sec, 5595569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 40/414 34/2000 RefineWMG-PT-100100-CTLFireability-2024-05 2545685 m, 62376 m/sec, 6376847 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 45/414 38/2000 RefineWMG-PT-100100-CTLFireability-2024-05 2857141 m, 62291 m/sec, 7157066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 50/414 42/2000 RefineWMG-PT-100100-CTLFireability-2024-05 3169482 m, 62468 m/sec, 7939412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 55/414 47/2000 RefineWMG-PT-100100-CTLFireability-2024-05 3480843 m, 62272 m/sec, 8719417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 60/414 51/2000 RefineWMG-PT-100100-CTLFireability-2024-05 3789550 m, 61741 m/sec, 9492751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 65/414 55/2000 RefineWMG-PT-100100-CTLFireability-2024-05 4093977 m, 60885 m/sec, 10255342 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 70/414 59/2000 RefineWMG-PT-100100-CTLFireability-2024-05 4401875 m, 61579 m/sec, 11026604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 75/414 63/2000 RefineWMG-PT-100100-CTLFireability-2024-05 4709612 m, 61547 m/sec, 11797517 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 80/414 67/2000 RefineWMG-PT-100100-CTLFireability-2024-05 5017318 m, 61541 m/sec, 12568302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 85/414 71/2000 RefineWMG-PT-100100-CTLFireability-2024-05 5327985 m, 62133 m/sec, 13346519 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 90/414 75/2000 RefineWMG-PT-100100-CTLFireability-2024-05 5632468 m, 60896 m/sec, 14109239 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 95/414 79/2000 RefineWMG-PT-100100-CTLFireability-2024-05 5940556 m, 61617 m/sec, 14881023 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 100/414 84/2000 RefineWMG-PT-100100-CTLFireability-2024-05 6244593 m, 60807 m/sec, 15642675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 105/414 88/2000 RefineWMG-PT-100100-CTLFireability-2024-05 6556854 m, 62452 m/sec, 16424826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 110/414 92/2000 RefineWMG-PT-100100-CTLFireability-2024-05 6869408 m, 62510 m/sec, 17207793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 115/414 96/2000 RefineWMG-PT-100100-CTLFireability-2024-05 7179219 m, 61962 m/sec, 17983845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 120/414 100/2000 RefineWMG-PT-100100-CTLFireability-2024-05 7489068 m, 61969 m/sec, 18760023 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 125/414 104/2000 RefineWMG-PT-100100-CTLFireability-2024-05 7798998 m, 61986 m/sec, 19536422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 130/414 108/2000 RefineWMG-PT-100100-CTLFireability-2024-05 8106911 m, 61582 m/sec, 20307736 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 135/414 113/2000 RefineWMG-PT-100100-CTLFireability-2024-05 8418444 m, 62306 m/sec, 21088099 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 140/414 117/2000 RefineWMG-PT-100100-CTLFireability-2024-05 8730902 m, 62491 m/sec, 21870842 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 145/414 121/2000 RefineWMG-PT-100100-CTLFireability-2024-05 9044122 m, 62644 m/sec, 22655440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 150/414 125/2000 RefineWMG-PT-100100-CTLFireability-2024-05 9359060 m, 62987 m/sec, 23444356 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 155/414 129/2000 RefineWMG-PT-100100-CTLFireability-2024-05 9668845 m, 61957 m/sec, 24220360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 160/414 133/2000 RefineWMG-PT-100100-CTLFireability-2024-05 9977990 m, 61829 m/sec, 24994834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 165/414 137/2000 RefineWMG-PT-100100-CTLFireability-2024-05 10284178 m, 61237 m/sec, 25761825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 170/414 141/2000 RefineWMG-PT-100100-CTLFireability-2024-05 10589042 m, 60972 m/sec, 26525528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 175/414 145/2000 RefineWMG-PT-100100-CTLFireability-2024-05 10894968 m, 61185 m/sec, 27291807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-02: EXEG true state space /EXEG[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-100100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-100100-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-04: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-100100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 CTL EXCL 180/414 149/2000 RefineWMG-PT-100100-CTLFireability-2024-05 11196824 m, 60371 m/sec, 28047953 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 400 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-100100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RefineWMG-PT-100100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662341200754"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-100100.tgz
mv RefineWMG-PT-100100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;