About the Execution of LoLA for RefineWMG-PT-050051
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16203.563 | 110827.00 | 112874.00 | 523.50 | ???FF????T?????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662341100748.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RefineWMG-PT-050051, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662341100748
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 532K
-rw-r--r-- 1 mcc users 6.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 23 07:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 23 07:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 23 07:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 23 07:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.6K Apr 13 05:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 101K Apr 13 05:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.1K Apr 13 05:03 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 70K Apr 13 05:03 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:47 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:47 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 7 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 110K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-00
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-01
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-02
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-03
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-04
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-05
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-06
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-07
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-08
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-09
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-10
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-11
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-12
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-13
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-14
FORMULA_NAME RefineWMG-PT-050051-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717354358143
FORMULA RefineWMG-PT-050051-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-050051-LTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RefineWMG-PT-050051-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717354468970
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 18 (type EXCL) for 13 RefineWMG-PT-050051-LTLFireability-03
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 18 (type EXCL) for RefineWMG-PT-050051-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 54
[[35mlola[0m][I] fired transitions : 54
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 RefineWMG-PT-050051-LTLFireability-09
[[35mlola[0m][I] time limit : 150 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 61 (type FNDP) for 20 RefineWMG-PT-050051-LTLFireability-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 20 RefineWMG-PT-050051-LTLFireability-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for RefineWMG-PT-050051-LTLFireability-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 52
[[35mlola[0m][I] fired transitions : 51
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 20 RefineWMG-PT-050051-LTLFireability-04
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for RefineWMG-PT-050051-LTLFireability-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 61 (type FNDP) for RefineWMG-PT-050051-LTLFireability-04 (obsolete)
[[35mlola[0m][W] CANCELED task # 62 (type EQUN) for RefineWMG-PT-050051-LTLFireability-04 (obsolete)
[[35mlola[0m][I] FINISHED task # 61 (type FNDP) for RefineWMG-PT-050051-LTLFireability-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for RefineWMG-PT-050051-LTLFireability-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 3 RefineWMG-PT-050051-LTLFireability-01
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 38 RefineWMG-PT-050051-LTLFireability-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for RefineWMG-PT-050051-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 5/240 13/2000 RefineWMG-PT-050051-LTLFireability-01 1881639 m, 376327 m/sec, 2840855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 10/240 25/2000 RefineWMG-PT-050051-LTLFireability-01 3786629 m, 380998 m/sec, 5717015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 15/240 37/2000 RefineWMG-PT-050051-LTLFireability-01 5687509 m, 380176 m/sec, 8586949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 20/240 50/2000 RefineWMG-PT-050051-LTLFireability-01 7599980 m, 382494 m/sec, 11474418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 25/240 63/2000 RefineWMG-PT-050051-LTLFireability-01 9570551 m, 394114 m/sec, 14449583 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 30/240 75/2000 RefineWMG-PT-050051-LTLFireability-01 11500005 m, 385890 m/sec, 17362695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 35/240 88/2000 RefineWMG-PT-050051-LTLFireability-01 13437622 m, 387523 m/sec, 20288125 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 40/240 100/2000 RefineWMG-PT-050051-LTLFireability-01 15362100 m, 384895 m/sec, 23193681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 45/240 113/2000 RefineWMG-PT-050051-LTLFireability-01 17279066 m, 383393 m/sec, 26087958 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 50/240 125/2000 RefineWMG-PT-050051-LTLFireability-01 19180531 m, 380293 m/sec, 28958783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 55/240 137/2000 RefineWMG-PT-050051-LTLFireability-01 21083294 m, 380552 m/sec, 31831584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 60/240 150/2000 RefineWMG-PT-050051-LTLFireability-01 23025657 m, 388472 m/sec, 34764145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 65/240 162/2000 RefineWMG-PT-050051-LTLFireability-01 24936039 m, 382076 m/sec, 37648457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 70/240 174/2000 RefineWMG-PT-050051-LTLFireability-01 26812501 m, 375292 m/sec, 40481551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 75/240 186/2000 RefineWMG-PT-050051-LTLFireability-01 28680211 m, 373542 m/sec, 43301448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 80/240 199/2000 RefineWMG-PT-050051-LTLFireability-01 30541076 m, 372173 m/sec, 46110974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 85/240 211/2000 RefineWMG-PT-050051-LTLFireability-01 32470049 m, 385794 m/sec, 49023364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 90/240 224/2000 RefineWMG-PT-050051-LTLFireability-01 34392839 m, 384558 m/sec, 51926363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 95/240 236/2000 RefineWMG-PT-050051-LTLFireability-01 36321848 m, 385801 m/sec, 54838794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 100/240 249/2000 RefineWMG-PT-050051-LTLFireability-01 38243834 m, 384397 m/sec, 57740628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-03: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-050051-LTLFireability-04: AG false state space[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-050051-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-01: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-10: AU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-050051-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 LTL EXCL 105/240 261/2000 RefineWMG-PT-050051-LTLFireability-01 40159777 m, 383188 m/sec, 60633332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-050051"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RefineWMG-PT-050051, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662341100748"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-050051.tgz
mv RefineWMG-PT-050051 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;