About the Execution of LoLA for RefineWMG-PT-010011
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16175.296 | 116382.00 | 118101.00 | 487.70 | ??F????????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662341000698.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RefineWMG-PT-010011, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662341000698
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 452K
-rw-r--r-- 1 mcc users 7.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K May 19 07:14 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 19 16:22 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 23 07:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 23 07:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.4K Apr 13 04:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 72K Apr 13 04:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.7K Apr 13 04:55 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Apr 13 04:55 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:47 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:47 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 7 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 24K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-00
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-01
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-02
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-03
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-04
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-05
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-06
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-07
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-08
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-09
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-10
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2024-11
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2023-12
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2023-13
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2023-14
FORMULA_NAME RefineWMG-PT-010011-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717353333251
FORMULA RefineWMG-PT-010011-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717353449633
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 RefineWMG-PT-010011-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 49 (type FNDP) for 6 RefineWMG-PT-010011-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 50 (type EQUN) for 6 RefineWMG-PT-010011-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 49 (type FNDP) for RefineWMG-PT-010011-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 50 (type EQUN) for RefineWMG-PT-010011-CTLFireability-2024-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 50 (type EQUN) for RefineWMG-PT-010011-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for RefineWMG-PT-010011-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7244
[[35mlola[0m][I] fired transitions : 44871
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 RefineWMG-PT-010011-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for RefineWMG-PT-010011-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 RefineWMG-PT-010011-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for RefineWMG-PT-010011-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 96
[[35mlola[0m][I] fired transitions : 165
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 RefineWMG-PT-010011-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for RefineWMG-PT-010011-CTLFireability-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 360
[[35mlola[0m][I] fired transitions : 647
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 RefineWMG-PT-010011-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for RefineWMG-PT-010011-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 383
[[35mlola[0m][I] fired transitions : 622
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 RefineWMG-PT-010011-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 360 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for RefineWMG-PT-010011-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1364
[[35mlola[0m][I] fired transitions : 3957
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 RefineWMG-PT-010011-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 400 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 5/400 18/2000 RefineWMG-PT-010011-CTLFireability-2024-10 4024240 m, 804848 m/sec, 6219256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 10/400 34/2000 RefineWMG-PT-010011-CTLFireability-2024-10 7963022 m, 787756 m/sec, 12306462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 15/400 50/2000 RefineWMG-PT-010011-CTLFireability-2024-10 11779337 m, 763263 m/sec, 18204394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 20/400 66/2000 RefineWMG-PT-010011-CTLFireability-2024-10 15552190 m, 754570 m/sec, 24035177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 25/400 81/2000 RefineWMG-PT-010011-CTLFireability-2024-10 19246535 m, 738869 m/sec, 29744620 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 30/400 97/2000 RefineWMG-PT-010011-CTLFireability-2024-10 23075349 m, 765762 m/sec, 35661878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 35/400 113/2000 RefineWMG-PT-010011-CTLFireability-2024-10 26872146 m, 759359 m/sec, 41529654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 40/400 129/2000 RefineWMG-PT-010011-CTLFireability-2024-10 30626882 m, 750947 m/sec, 47332428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 45/400 144/2000 RefineWMG-PT-010011-CTLFireability-2024-10 34274325 m, 729488 m/sec, 52969380 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 50/400 158/2000 RefineWMG-PT-010011-CTLFireability-2024-10 37840333 m, 713201 m/sec, 58480487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 55/400 172/2000 RefineWMG-PT-010011-CTLFireability-2024-10 41321114 m, 696156 m/sec, 63859877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 60/400 187/2000 RefineWMG-PT-010011-CTLFireability-2024-10 44894846 m, 714746 m/sec, 69382911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 65/400 201/2000 RefineWMG-PT-010011-CTLFireability-2024-10 48482353 m, 717501 m/sec, 74927243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 70/400 215/2000 RefineWMG-PT-010011-CTLFireability-2024-10 52052119 m, 713953 m/sec, 80444147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 75/400 229/2000 RefineWMG-PT-010011-CTLFireability-2024-10 55629102 m, 715396 m/sec, 85972213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 80/400 244/2000 RefineWMG-PT-010011-CTLFireability-2024-10 59219933 m, 718166 m/sec, 91521681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 85/400 259/2000 RefineWMG-PT-010011-CTLFireability-2024-10 62930932 m, 742199 m/sec, 97256863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 90/400 273/2000 RefineWMG-PT-010011-CTLFireability-2024-10 66556244 m, 725062 m/sec, 102859615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 95/400 288/2000 RefineWMG-PT-010011-CTLFireability-2024-10 70152040 m, 719159 m/sec, 108416747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 100/400 302/2000 RefineWMG-PT-010011-CTLFireability-2024-10 73680326 m, 705657 m/sec, 113869556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 302
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 105/400 316/2000 RefineWMG-PT-010011-CTLFireability-2024-10 77151263 m, 694187 m/sec, 119233743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 316
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 110/400 330/2000 RefineWMG-PT-010011-CTLFireability-2024-10 80638446 m, 697436 m/sec, 124623023 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 330
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-02: AG false findpath[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mRefineWMG-PT-010011-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mRefineWMG-PT-010011-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] RefineWMG-PT-010011-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 115/400 343/2000 RefineWMG-PT-010011-CTLFireability-2024-10 84149857 m, 702282 m/sec, 130049760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-010011"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RefineWMG-PT-010011, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662341000698"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-010011.tgz
mv RefineWMG-PT-010011 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;