About the Execution of LoLA for Referendum-COL-1000
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
5404.911 | 3600000.00 | 4269104.00 | 9988.40 | ????F??????????F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662340700570.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Referendum-COL-1000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662340700570
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 588K
-rw-r--r-- 1 mcc users 9.3K Apr 11 18:18 CTLCardinality.txt
-rw-r--r-- 1 mcc users 98K Apr 11 18:18 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Apr 11 16:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Apr 11 16:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 23 07:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 23 07:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 11 21:30 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 151K Apr 11 21:30 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 11 18:59 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 100K Apr 11 18:59 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:47 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:47 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 5 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 41K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-00
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-01
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-02
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-03
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-04
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-05
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-06
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-07
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-08
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-09
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-10
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-11
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-12
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-13
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-14
FORMULA_NAME Referendum-COL-1000-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717339579203
FORMULA Referendum-COL-1000-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Referendum-COL-1000-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Places: 3001, Transitions: 2001
[[35mlola[0m][I] LAUNCH task # 14 (type SKEL/CNST) for 12 Referendum-COL-1000-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 67 (type SKEL/CNST) for 65 Referendum-COL-1000-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 14 (type SKEL/CNST) for Referendum-COL-1000-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 67 (type SKEL/CNST) for Referendum-COL-1000-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] findlow criterion satisfied
[[35mlola[0m][I] Time for checking findlow: 1
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/SRCH) for 21 Referendum-COL-1000-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/SRCH) for 62 Referendum-COL-1000-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/SRCH) for Referendum-COL-1000-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/SRCH) for Referendum-COL-1000-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1002
[[35mlola[0m][I] fired transitions : 4006
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] planning for Referendum-COL-1000-CTLFireability-2024-14 stopped (result already fixed).
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 21 Referendum-COL-1000-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1000
[[35mlola[0m][I] fired transitions : 999
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 Referendum-COL-1000-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 Referendum-COL-1000-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 2/239 1/2000 Referendum-COL-1000-CTLFireability-2024-02 23697 m, 4739 m/sec, 320767 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 7/239 1/2000 Referendum-COL-1000-CTLFireability-2024-02 77185 m, 10697 m/sec, 1209186 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 12/239 1/2000 Referendum-COL-1000-CTLFireability-2024-02 125878 m, 9738 m/sec, 2095139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 17/239 2/2000 Referendum-COL-1000-CTLFireability-2024-02 175835 m, 9991 m/sec, 2973612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 22/239 2/2000 Referendum-COL-1000-CTLFireability-2024-02 222130 m, 9259 m/sec, 3858324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 27/239 2/2000 Referendum-COL-1000-CTLFireability-2024-02 264831 m, 8540 m/sec, 4740587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 32/239 2/2000 Referendum-COL-1000-CTLFireability-2024-02 314857 m, 10005 m/sec, 5615222 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 37/239 3/2000 Referendum-COL-1000-CTLFireability-2024-02 360088 m, 9046 m/sec, 6489466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 42/239 3/2000 Referendum-COL-1000-CTLFireability-2024-02 403597 m, 8701 m/sec, 7368231 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 47/239 3/2000 Referendum-COL-1000-CTLFireability-2024-02 447703 m, 8821 m/sec, 8246617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 52/239 3/2000 Referendum-COL-1000-CTLFireability-2024-02 489147 m, 8288 m/sec, 9126074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 57/239 4/2000 Referendum-COL-1000-CTLFireability-2024-02 528602 m, 7891 m/sec, 10006901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 62/239 4/2000 Referendum-COL-1000-CTLFireability-2024-02 578294 m, 9938 m/sec, 10882990 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 67/239 4/2000 Referendum-COL-1000-CTLFireability-2024-02 623321 m, 9005 m/sec, 11758030 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 72/239 5/2000 Referendum-COL-1000-CTLFireability-2024-02 667006 m, 8737 m/sec, 12633736 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 77/239 5/2000 Referendum-COL-1000-CTLFireability-2024-02 710810 m, 8760 m/sec, 13509169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 82/239 5/2000 Referendum-COL-1000-CTLFireability-2024-02 751970 m, 8232 m/sec, 14384620 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 87/239 5/2000 Referendum-COL-1000-CTLFireability-2024-02 790869 m, 7779 m/sec, 15258543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 92/239 6/2000 Referendum-COL-1000-CTLFireability-2024-02 835709 m, 8968 m/sec, 16134442 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 97/239 6/2000 Referendum-COL-1000-CTLFireability-2024-02 877240 m, 8306 m/sec, 17008197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 102/239 6/2000 Referendum-COL-1000-CTLFireability-2024-02 915507 m, 7653 m/sec, 17877888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 107/239 6/2000 Referendum-COL-1000-CTLFireability-2024-02 956370 m, 8172 m/sec, 18748134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 112/239 7/2000 Referendum-COL-1000-CTLFireability-2024-02 994496 m, 7625 m/sec, 19619152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 117/239 7/2000 Referendum-COL-1000-CTLFireability-2024-02 1031071 m, 7315 m/sec, 20489452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 122/239 7/2000 Referendum-COL-1000-CTLFireability-2024-02 1073451 m, 8476 m/sec, 21359424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 127/239 7/2000 Referendum-COL-1000-CTLFireability-2024-02 1119930 m, 9295 m/sec, 22228781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 132/239 8/2000 Referendum-COL-1000-CTLFireability-2024-02 1164088 m, 8831 m/sec, 23098051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 137/239 8/2000 Referendum-COL-1000-CTLFireability-2024-02 1208076 m, 8797 m/sec, 23968103 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 142/239 8/2000 Referendum-COL-1000-CTLFireability-2024-02 1249827 m, 8350 m/sec, 24837811 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 147/239 8/2000 Referendum-COL-1000-CTLFireability-2024-02 1290552 m, 8145 m/sec, 25707010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 152/239 9/2000 Referendum-COL-1000-CTLFireability-2024-02 1331789 m, 8247 m/sec, 26575388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 157/239 9/2000 Referendum-COL-1000-CTLFireability-2024-02 1373961 m, 8434 m/sec, 27445142 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 162/239 9/2000 Referendum-COL-1000-CTLFireability-2024-02 1415084 m, 8224 m/sec, 28315479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 167/239 9/2000 Referendum-COL-1000-CTLFireability-2024-02 1454126 m, 7808 m/sec, 29184408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 172/239 9/2000 Referendum-COL-1000-CTLFireability-2024-02 1493787 m, 7932 m/sec, 30054763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 177/239 10/2000 Referendum-COL-1000-CTLFireability-2024-02 1531626 m, 7567 m/sec, 30925610 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 182/239 10/2000 Referendum-COL-1000-CTLFireability-2024-02 1567094 m, 7093 m/sec, 31795966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 187/239 10/2000 Referendum-COL-1000-CTLFireability-2024-02 1610287 m, 8638 m/sec, 32669613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 192/239 10/2000 Referendum-COL-1000-CTLFireability-2024-02 1652327 m, 8408 m/sec, 33543202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 197/239 11/2000 Referendum-COL-1000-CTLFireability-2024-02 1692003 m, 7935 m/sec, 34416122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 202/239 11/2000 Referendum-COL-1000-CTLFireability-2024-02 1732074 m, 8014 m/sec, 35288768 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 207/239 11/2000 Referendum-COL-1000-CTLFireability-2024-02 1769912 m, 7567 m/sec, 36161040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 212/239 11/2000 Referendum-COL-1000-CTLFireability-2024-02 1807939 m, 7605 m/sec, 37033497 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 217/239 11/2000 Referendum-COL-1000-CTLFireability-2024-02 1844122 m, 7236 m/sec, 37903697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 222/239 12/2000 Referendum-COL-1000-CTLFireability-2024-02 1884242 m, 8024 m/sec, 38774399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 227/239 12/2000 Referendum-COL-1000-CTLFireability-2024-02 1922182 m, 7588 m/sec, 39645304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 232/239 12/2000 Referendum-COL-1000-CTLFireability-2024-02 1957872 m, 7138 m/sec, 40514986 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 237/239 12/2000 Referendum-COL-1000-CTLFireability-2024-02 1994757 m, 7377 m/sec, 41385808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 59 Referendum-COL-1000-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 Referendum-COL-1000-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 3355 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1001
[[35mlola[0m][I] fired transitions : 2001
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 5/239 1/5 Referendum-COL-1000-CTLFireability-2024-02 56752 m, -387601 m/sec, 862763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 10/239 1/5 Referendum-COL-1000-CTLFireability-2024-02 107585 m, 10166 m/sec, 1747104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 15/239 1/5 Referendum-COL-1000-CTLFireability-2024-02 156542 m, 9791 m/sec, 2628384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 20/239 2/5 Referendum-COL-1000-CTLFireability-2024-02 203754 m, 9442 m/sec, 3509341 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 25/239 2/5 Referendum-COL-1000-CTLFireability-2024-02 248578 m, 8964 m/sec, 4393118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 30/239 2/5 Referendum-COL-1000-CTLFireability-2024-02 295755 m, 9435 m/sec, 5273013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 35/239 3/5 Referendum-COL-1000-CTLFireability-2024-02 343172 m, 9483 m/sec, 6153958 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 40/239 3/5 Referendum-COL-1000-CTLFireability-2024-02 386650 m, 8695 m/sec, 7033641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 45/239 3/5 Referendum-COL-1000-CTLFireability-2024-02 431470 m, 8964 m/sec, 7912806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 50/239 3/5 Referendum-COL-1000-CTLFireability-2024-02 473757 m, 8457 m/sec, 8793613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 55/239 4/5 Referendum-COL-1000-CTLFireability-2024-02 513707 m, 7990 m/sec, 9674563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 60/239 4/5 Referendum-COL-1000-CTLFireability-2024-02 560232 m, 9305 m/sec, 10551995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 65/239 4/5 Referendum-COL-1000-CTLFireability-2024-02 606767 m, 9307 m/sec, 11426902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 70/239 4/5 Referendum-COL-1000-CTLFireability-2024-02 649996 m, 8645 m/sec, 12302325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 75/239 5/5 Referendum-COL-1000-CTLFireability-2024-02 694699 m, 8940 m/sec, 13176184 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 80/239 5/5 Referendum-COL-1000-CTLFireability-2024-02 736599 m, 8380 m/sec, 14051815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 85/239 5/5 Referendum-COL-1000-CTLFireability-2024-02 776292 m, 7938 m/sec, 14927600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 7 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 56 Referendum-COL-1000-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 251 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 5/251 1/2000 Referendum-COL-1000-CTLFireability-2024-12 56238 m, 11247 m/sec, 853952 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 10/251 1/2000 Referendum-COL-1000-CTLFireability-2024-12 106218 m, 9996 m/sec, 1720484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 15/251 1/2000 Referendum-COL-1000-CTLFireability-2024-12 154273 m, 9611 m/sec, 2585362 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 20/251 2/2000 Referendum-COL-1000-CTLFireability-2024-12 200168 m, 9179 m/sec, 3447360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 25/251 2/2000 Referendum-COL-1000-CTLFireability-2024-12 244654 m, 8897 m/sec, 4310819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 30/251 2/2000 Referendum-COL-1000-CTLFireability-2024-12 290333 m, 9135 m/sec, 5165527 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 35/251 3/2000 Referendum-COL-1000-CTLFireability-2024-12 335931 m, 9119 m/sec, 6019541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 40/251 3/2000 Referendum-COL-1000-CTLFireability-2024-12 379066 m, 8627 m/sec, 6871831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 45/251 3/2000 Referendum-COL-1000-CTLFireability-2024-12 422168 m, 8620 m/sec, 7726216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 50/251 3/2000 Referendum-COL-1000-CTLFireability-2024-12 463373 m, 8241 m/sec, 8584484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 55/251 4/2000 Referendum-COL-1000-CTLFireability-2024-12 503668 m, 8059 m/sec, 9443755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 60/251 4/2000 Referendum-COL-1000-CTLFireability-2024-12 546480 m, 8562 m/sec, 10301060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 65/251 4/2000 Referendum-COL-1000-CTLFireability-2024-12 591642 m, 9032 m/sec, 11153162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 70/251 4/2000 Referendum-COL-1000-CTLFireability-2024-12 636107 m, 8893 m/sec, 12006493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 75/251 5/2000 Referendum-COL-1000-CTLFireability-2024-12 678706 m, 8519 m/sec, 12856476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 80/251 5/2000 Referendum-COL-1000-CTLFireability-2024-12 719635 m, 8185 m/sec, 13707049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 85/251 5/2000 Referendum-COL-1000-CTLFireability-2024-12 760004 m, 8073 m/sec, 14558666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 90/251 5/2000 Referendum-COL-1000-CTLFireability-2024-12 799378 m, 7874 m/sec, 15411075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 95/251 6/2000 Referendum-COL-1000-CTLFireability-2024-12 842090 m, 8542 m/sec, 16266117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 100/251 6/2000 Referendum-COL-1000-CTLFireability-2024-12 882306 m, 8043 m/sec, 17120138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 105/251 6/2000 Referendum-COL-1000-CTLFireability-2024-12 919336 m, 7406 m/sec, 17970828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 110/251 6/2000 Referendum-COL-1000-CTLFireability-2024-12 959827 m, 8098 m/sec, 18824867 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 115/251 7/2000 Referendum-COL-1000-CTLFireability-2024-12 997129 m, 7460 m/sec, 19679161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 120/251 7/2000 Referendum-COL-1000-CTLFireability-2024-12 1032721 m, 7118 m/sec, 20533125 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 125/251 7/2000 Referendum-COL-1000-CTLFireability-2024-12 1074861 m, 8428 m/sec, 21384789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 130/251 7/2000 Referendum-COL-1000-CTLFireability-2024-12 1120125 m, 9052 m/sec, 22232205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 135/251 8/2000 Referendum-COL-1000-CTLFireability-2024-12 1163187 m, 8612 m/sec, 23076805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 140/251 8/2000 Referendum-COL-1000-CTLFireability-2024-12 1205677 m, 8498 m/sec, 23921184 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 145/251 8/2000 Referendum-COL-1000-CTLFireability-2024-12 1245919 m, 8048 m/sec, 24766546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 150/251 8/2000 Referendum-COL-1000-CTLFireability-2024-12 1286210 m, 8058 m/sec, 25611278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 155/251 8/2000 Referendum-COL-1000-CTLFireability-2024-12 1325475 m, 7853 m/sec, 26455265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 160/251 9/2000 Referendum-COL-1000-CTLFireability-2024-12 1368059 m, 8516 m/sec, 27313715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 165/251 9/2000 Referendum-COL-1000-CTLFireability-2024-12 1408562 m, 8100 m/sec, 28176740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 170/251 9/2000 Referendum-COL-1000-CTLFireability-2024-12 1446819 m, 7651 m/sec, 29040265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 175/251 9/2000 Referendum-COL-1000-CTLFireability-2024-12 1487317 m, 8099 m/sec, 29905242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 180/251 10/2000 Referendum-COL-1000-CTLFireability-2024-12 1524609 m, 7458 m/sec, 30767512 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 185/251 10/2000 Referendum-COL-1000-CTLFireability-2024-12 1560734 m, 7225 m/sec, 31632816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 190/251 10/2000 Referendum-COL-1000-CTLFireability-2024-12 1601804 m, 8214 m/sec, 32498577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 195/251 10/2000 Referendum-COL-1000-CTLFireability-2024-12 1643440 m, 8327 m/sec, 33365923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 200/251 11/2000 Referendum-COL-1000-CTLFireability-2024-12 1684039 m, 8119 m/sec, 34233205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 205/251 11/2000 Referendum-COL-1000-CTLFireability-2024-12 1723059 m, 7804 m/sec, 35095086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 210/251 11/2000 Referendum-COL-1000-CTLFireability-2024-12 1761912 m, 7770 m/sec, 35962191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 215/251 11/2000 Referendum-COL-1000-CTLFireability-2024-12 1799394 m, 7496 m/sec, 36829795 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 220/251 11/2000 Referendum-COL-1000-CTLFireability-2024-12 1834096 m, 6940 m/sec, 37694086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 225/251 12/2000 Referendum-COL-1000-CTLFireability-2024-12 1874730 m, 8126 m/sec, 38558384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 230/251 12/2000 Referendum-COL-1000-CTLFireability-2024-12 1912633 m, 7580 m/sec, 39425062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 235/251 12/2000 Referendum-COL-1000-CTLFireability-2024-12 1948904 m, 7254 m/sec, 40289553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 240/251 12/2000 Referendum-COL-1000-CTLFireability-2024-12 1984777 m, 7174 m/sec, 41151302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 245/251 12/2000 Referendum-COL-1000-CTLFireability-2024-12 2020566 m, 7157 m/sec, 42015110 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 CTL EXCL 250/251 13/2000 Referendum-COL-1000-CTLFireability-2024-12 2055056 m, 6898 m/sec, 42877819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 57 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 Referendum-COL-1000-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 250 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 56 Referendum-COL-1000-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 3010 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 5/250 1/2000 Referendum-COL-1000-CTLFireability-2024-11 56186 m, 11237 m/sec, 852857 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 5/3010 1/5 Referendum-COL-1000-CTLFireability-2024-12 55302 m, -399950 m/sec, 837084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 10/250 1/2000 Referendum-COL-1000-CTLFireability-2024-11 106273 m, 10017 m/sec, 1721493 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 10/231 1/5 Referendum-COL-1000-CTLFireability-2024-12 104924 m, 9924 m/sec, 1697256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 15/250 1/2000 Referendum-COL-1000-CTLFireability-2024-11 154464 m, 9638 m/sec, 2589066 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 15/231 1/5 Referendum-COL-1000-CTLFireability-2024-12 152491 m, 9513 m/sec, 2555761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 20/250 2/2000 Referendum-COL-1000-CTLFireability-2024-11 200500 m, 9207 m/sec, 3452740 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 20/231 2/5 Referendum-COL-1000-CTLFireability-2024-12 197925 m, 9086 m/sec, 3412751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 25/250 2/2000 Referendum-COL-1000-CTLFireability-2024-11 245061 m, 8912 m/sec, 4319306 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 25/231 2/5 Referendum-COL-1000-CTLFireability-2024-12 242750 m, 8965 m/sec, 4270630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 30/250 2/2000 Referendum-COL-1000-CTLFireability-2024-11 291202 m, 9228 m/sec, 5181962 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 30/231 2/5 Referendum-COL-1000-CTLFireability-2024-12 288108 m, 9071 m/sec, 5126686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 35/250 3/2000 Referendum-COL-1000-CTLFireability-2024-11 337164 m, 9192 m/sec, 6042672 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 35/231 3/5 Referendum-COL-1000-CTLFireability-2024-12 333717 m, 9121 m/sec, 5979701 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 40/250 3/2000 Referendum-COL-1000-CTLFireability-2024-11 380825 m, 8732 m/sec, 6907297 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 40/231 3/5 Referendum-COL-1000-CTLFireability-2024-12 377154 m, 8687 m/sec, 6832855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 45/250 3/2000 Referendum-COL-1000-CTLFireability-2024-11 424248 m, 8684 m/sec, 7769877 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 45/231 3/5 Referendum-COL-1000-CTLFireability-2024-12 420056 m, 8580 m/sec, 7683473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 50/250 3/2000 Referendum-COL-1000-CTLFireability-2024-11 465973 m, 8345 m/sec, 8634718 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 50/231 3/5 Referendum-COL-1000-CTLFireability-2024-12 460807 m, 8150 m/sec, 8537578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 55/250 4/2000 Referendum-COL-1000-CTLFireability-2024-11 506105 m, 8026 m/sec, 9499727 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 55/231 4/5 Referendum-COL-1000-CTLFireability-2024-12 501273 m, 8093 m/sec, 9391651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 60/250 4/2000 Referendum-COL-1000-CTLFireability-2024-11 549676 m, 8714 m/sec, 10359811 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 60/231 4/5 Referendum-COL-1000-CTLFireability-2024-12 543046 m, 8354 m/sec, 10244014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 65/250 4/2000 Referendum-COL-1000-CTLFireability-2024-11 595558 m, 9176 m/sec, 11217340 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 65/231 4/5 Referendum-COL-1000-CTLFireability-2024-12 588681 m, 9127 m/sec, 11092903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 70/250 4/2000 Referendum-COL-1000-CTLFireability-2024-11 639265 m, 8741 m/sec, 12074948 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 70/231 4/5 Referendum-COL-1000-CTLFireability-2024-12 633010 m, 8865 m/sec, 11942505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 75/250 5/2000 Referendum-COL-1000-CTLFireability-2024-11 682531 m, 8653 m/sec, 12932780 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 75/231 5/5 Referendum-COL-1000-CTLFireability-2024-12 675309 m, 8459 m/sec, 12791479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 80/250 5/2000 Referendum-COL-1000-CTLFireability-2024-11 723556 m, 8205 m/sec, 13790885 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 80/231 5/5 Referendum-COL-1000-CTLFireability-2024-12 716752 m, 8288 m/sec, 13640413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 85/250 5/2000 Referendum-COL-1000-CTLFireability-2024-11 764157 m, 8120 m/sec, 14649950 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 85/231 5/5 Referendum-COL-1000-CTLFireability-2024-12 756672 m, 7984 m/sec, 14489915 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 90/250 5/2000 Referendum-COL-1000-CTLFireability-2024-11 804317 m, 8032 m/sec, 15507941 t fired, .
[[35mlola[0m][.] 57 CTL EXCL 90/231 5/5 Referendum-COL-1000-CTLFireability-2024-12 795409 m, 7747 m/sec, 15340005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 57 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 95/250 6/2000 Referendum-COL-1000-CTLFireability-2024-11 847039 m, 8544 m/sec, 16375096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 100/250 6/2000 Referendum-COL-1000-CTLFireability-2024-11 888308 m, 8253 m/sec, 17253202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 105/250 6/2000 Referendum-COL-1000-CTLFireability-2024-11 927664 m, 7871 m/sec, 18130916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 110/250 6/2000 Referendum-COL-1000-CTLFireability-2024-11 967607 m, 7988 m/sec, 19005399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 115/250 7/2000 Referendum-COL-1000-CTLFireability-2024-11 1006031 m, 7684 m/sec, 19884212 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 120/250 7/2000 Referendum-COL-1000-CTLFireability-2024-11 1041785 m, 7150 m/sec, 20760593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 125/250 7/2000 Referendum-COL-1000-CTLFireability-2024-11 1088569 m, 9356 m/sec, 21631207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 130/250 7/2000 Referendum-COL-1000-CTLFireability-2024-11 1134467 m, 9179 m/sec, 22498357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 135/250 8/2000 Referendum-COL-1000-CTLFireability-2024-11 1176521 m, 8410 m/sec, 23364083 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 140/250 8/2000 Referendum-COL-1000-CTLFireability-2024-11 1221022 m, 8900 m/sec, 24227860 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 145/250 8/2000 Referendum-COL-1000-CTLFireability-2024-11 1262413 m, 8278 m/sec, 25097432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 150/250 8/2000 Referendum-COL-1000-CTLFireability-2024-11 1301990 m, 7915 m/sec, 25971355 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 155/250 9/2000 Referendum-COL-1000-CTLFireability-2024-11 1344863 m, 8574 m/sec, 26843521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 160/250 9/2000 Referendum-COL-1000-CTLFireability-2024-11 1387162 m, 8459 m/sec, 27713581 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 165/250 9/2000 Referendum-COL-1000-CTLFireability-2024-11 1427097 m, 7987 m/sec, 28588062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 170/250 9/2000 Referendum-COL-1000-CTLFireability-2024-11 1467162 m, 8013 m/sec, 29462480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 175/250 10/2000 Referendum-COL-1000-CTLFireability-2024-11 1505481 m, 7663 m/sec, 30333450 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 180/250 10/2000 Referendum-COL-1000-CTLFireability-2024-11 1542917 m, 7487 m/sec, 31201087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 185/250 10/2000 Referendum-COL-1000-CTLFireability-2024-11 1578453 m, 7107 m/sec, 32055590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 190/250 10/2000 Referendum-COL-1000-CTLFireability-2024-11 1622096 m, 8728 m/sec, 32910657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 195/250 10/2000 Referendum-COL-1000-CTLFireability-2024-11 1662873 m, 8155 m/sec, 33766716 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 200/250 11/2000 Referendum-COL-1000-CTLFireability-2024-11 1700558 m, 7537 m/sec, 34621080 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 205/250 11/2000 Referendum-COL-1000-CTLFireability-2024-11 1740515 m, 7991 m/sec, 35477066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 210/250 11/2000 Referendum-COL-1000-CTLFireability-2024-11 1778025 m, 7502 m/sec, 36333199 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 215/250 11/2000 Referendum-COL-1000-CTLFireability-2024-11 1814665 m, 7328 m/sec, 37194651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 220/250 12/2000 Referendum-COL-1000-CTLFireability-2024-11 1851991 m, 7465 m/sec, 38067475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 225/250 12/2000 Referendum-COL-1000-CTLFireability-2024-11 1891461 m, 7894 m/sec, 38939104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 230/250 12/2000 Referendum-COL-1000-CTLFireability-2024-11 1928933 m, 7494 m/sec, 39805635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 235/250 12/2000 Referendum-COL-1000-CTLFireability-2024-11 1963662 m, 6945 m/sec, 40667015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 240/250 12/2000 Referendum-COL-1000-CTLFireability-2024-11 2000128 m, 7293 m/sec, 41523266 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 245/250 13/2000 Referendum-COL-1000-CTLFireability-2024-11 2034651 m, 6904 m/sec, 42380292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 250/250 13/2000 Referendum-COL-1000-CTLFireability-2024-11 2068822 m, 6834 m/sec, 43237371 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 54 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 Referendum-COL-1000-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 250 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 Referendum-COL-1000-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 2755 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 5/250 1/2000 Referendum-COL-1000-CTLFireability-2024-10 56133 m, 11226 m/sec, 851784 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 5/2755 1/5 Referendum-COL-1000-CTLFireability-2024-11 56113 m, -402541 m/sec, 851382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 10/250 1/2000 Referendum-COL-1000-CTLFireability-2024-10 106284 m, 10030 m/sec, 1721697 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 10/229 1/5 Referendum-COL-1000-CTLFireability-2024-11 106215 m, 10020 m/sec, 1720413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 15/250 1/2000 Referendum-COL-1000-CTLFireability-2024-10 154547 m, 9652 m/sec, 2590757 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 15/229 1/5 Referendum-COL-1000-CTLFireability-2024-11 154374 m, 9631 m/sec, 2587267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 20/250 2/2000 Referendum-COL-1000-CTLFireability-2024-10 200879 m, 9266 m/sec, 3459195 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 20/229 2/5 Referendum-COL-1000-CTLFireability-2024-11 200567 m, 9238 m/sec, 3453935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 25/250 2/2000 Referendum-COL-1000-CTLFireability-2024-10 245506 m, 8925 m/sec, 4329215 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 25/229 2/5 Referendum-COL-1000-CTLFireability-2024-11 245172 m, 8921 m/sec, 4321781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 30/250 2/2000 Referendum-COL-1000-CTLFireability-2024-10 291863 m, 9271 m/sec, 5195499 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 30/229 2/5 Referendum-COL-1000-CTLFireability-2024-11 291435 m, 9252 m/sec, 5186623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 35/250 3/2000 Referendum-COL-1000-CTLFireability-2024-10 338009 m, 9229 m/sec, 6056708 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 35/229 3/5 Referendum-COL-1000-CTLFireability-2024-11 337397 m, 9192 m/sec, 6046437 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 40/250 3/2000 Referendum-COL-1000-CTLFireability-2024-10 381361 m, 8670 m/sec, 6918586 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 40/229 3/5 Referendum-COL-1000-CTLFireability-2024-11 380922 m, 8705 m/sec, 6909363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 45/250 3/2000 Referendum-COL-1000-CTLFireability-2024-10 424738 m, 8675 m/sec, 7780843 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 45/229 3/5 Referendum-COL-1000-CTLFireability-2024-11 424300 m, 8675 m/sec, 7771028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 50/250 3/2000 Referendum-COL-1000-CTLFireability-2024-10 466489 m, 8350 m/sec, 8644731 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 50/229 3/5 Referendum-COL-1000-CTLFireability-2024-11 465916 m, 8323 m/sec, 8633748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 55/250 4/2000 Referendum-COL-1000-CTLFireability-2024-10 506515 m, 8005 m/sec, 9509545 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 55/229 4/5 Referendum-COL-1000-CTLFireability-2024-11 506028 m, 8022 m/sec, 9497945 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 60/250 4/2000 Referendum-COL-1000-CTLFireability-2024-10 550220 m, 8741 m/sec, 10369047 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 60/229 4/5 Referendum-COL-1000-CTLFireability-2024-11 549531 m, 8700 m/sec, 10356786 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 65/250 4/2000 Referendum-COL-1000-CTLFireability-2024-10 595827 m, 9121 m/sec, 11221933 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 65/229 4/5 Referendum-COL-1000-CTLFireability-2024-11 595093 m, 9112 m/sec, 11210046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 70/250 4/2000 Referendum-COL-1000-CTLFireability-2024-10 639454 m, 8725 m/sec, 12079641 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 70/229 4/5 Referendum-COL-1000-CTLFireability-2024-11 638919 m, 8765 m/sec, 12067245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 75/250 5/2000 Referendum-COL-1000-CTLFireability-2024-10 682749 m, 8659 m/sec, 12937316 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 75/229 5/5 Referendum-COL-1000-CTLFireability-2024-11 682129 m, 8642 m/sec, 12924895 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 80/250 5/2000 Referendum-COL-1000-CTLFireability-2024-10 723785 m, 8207 m/sec, 13795248 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 80/229 5/5 Referendum-COL-1000-CTLFireability-2024-11 723142 m, 8202 m/sec, 13783569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 85/250 5/2000 Referendum-COL-1000-CTLFireability-2024-10 764330 m, 8109 m/sec, 14653731 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 85/229 5/5 Referendum-COL-1000-CTLFireability-2024-11 763765 m, 8124 m/sec, 14641753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 90/250 5/2000 Referendum-COL-1000-CTLFireability-2024-10 804444 m, 8022 m/sec, 15509827 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 90/229 5/5 Referendum-COL-1000-CTLFireability-2024-11 803663 m, 7979 m/sec, 15496730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 54 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 95/250 6/2000 Referendum-COL-1000-CTLFireability-2024-10 846763 m, 8463 m/sec, 16369406 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 100/250 6/2000 Referendum-COL-1000-CTLFireability-2024-10 887116 m, 8070 m/sec, 17229299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 105/250 6/2000 Referendum-COL-1000-CTLFireability-2024-10 925531 m, 7683 m/sec, 18088063 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 110/250 6/2000 Referendum-COL-1000-CTLFireability-2024-10 965332 m, 7960 m/sec, 18948412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 115/250 7/2000 Referendum-COL-1000-CTLFireability-2024-10 1002704 m, 7474 m/sec, 19807934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 120/250 7/2000 Referendum-COL-1000-CTLFireability-2024-10 1038159 m, 7091 m/sec, 20665659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 125/250 7/2000 Referendum-COL-1000-CTLFireability-2024-10 1081845 m, 8737 m/sec, 21518244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 130/250 7/2000 Referendum-COL-1000-CTLFireability-2024-10 1127703 m, 9171 m/sec, 22370149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 135/250 8/2000 Referendum-COL-1000-CTLFireability-2024-10 1170179 m, 8495 m/sec, 23222037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 140/250 8/2000 Referendum-COL-1000-CTLFireability-2024-10 1212957 m, 8555 m/sec, 24074136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 145/250 8/2000 Referendum-COL-1000-CTLFireability-2024-10 1254358 m, 8280 m/sec, 24929155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 150/250 8/2000 Referendum-COL-1000-CTLFireability-2024-10 1293755 m, 7879 m/sec, 25781933 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 155/250 9/2000 Referendum-COL-1000-CTLFireability-2024-10 1334873 m, 8223 m/sec, 26635052 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 160/250 9/2000 Referendum-COL-1000-CTLFireability-2024-10 1375777 m, 8180 m/sec, 27488195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 165/250 9/2000 Referendum-COL-1000-CTLFireability-2024-10 1416322 m, 8109 m/sec, 28342299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 170/250 9/2000 Referendum-COL-1000-CTLFireability-2024-10 1454644 m, 7664 m/sec, 29195462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 175/250 9/2000 Referendum-COL-1000-CTLFireability-2024-10 1493587 m, 7788 m/sec, 30050197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 180/250 10/2000 Referendum-COL-1000-CTLFireability-2024-10 1530790 m, 7440 m/sec, 30905857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 185/250 10/2000 Referendum-COL-1000-CTLFireability-2024-10 1565612 m, 6964 m/sec, 31759899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 190/250 10/2000 Referendum-COL-1000-CTLFireability-2024-10 1607246 m, 8326 m/sec, 32614473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 195/250 10/2000 Referendum-COL-1000-CTLFireability-2024-10 1648807 m, 8312 m/sec, 33470863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 200/250 11/2000 Referendum-COL-1000-CTLFireability-2024-10 1687967 m, 7832 m/sec, 34326351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 205/250 11/2000 Referendum-COL-1000-CTLFireability-2024-10 1727226 m, 7851 m/sec, 35182180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 210/250 11/2000 Referendum-COL-1000-CTLFireability-2024-10 1765077 m, 7570 m/sec, 36036962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 215/250 11/2000 Referendum-COL-1000-CTLFireability-2024-10 1801825 m, 7349 m/sec, 36891389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 220/250 11/2000 Referendum-COL-1000-CTLFireability-2024-10 1835853 m, 6805 m/sec, 37745154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 225/250 12/2000 Referendum-COL-1000-CTLFireability-2024-10 1876630 m, 8155 m/sec, 38601446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 230/250 12/2000 Referendum-COL-1000-CTLFireability-2024-10 1914009 m, 7475 m/sec, 39457332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 235/250 12/2000 Referendum-COL-1000-CTLFireability-2024-10 1949739 m, 7146 m/sec, 40311697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 240/250 12/2000 Referendum-COL-1000-CTLFireability-2024-10 1985478 m, 7147 m/sec, 41167277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 245/250 12/2000 Referendum-COL-1000-CTLFireability-2024-10 2020944 m, 7093 m/sec, 42024020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 51 CTL EXCL 250/250 13/2000 Referendum-COL-1000-CTLFireability-2024-10 2055166 m, 6844 m/sec, 42880721 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 51 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 4 0 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 35 Referendum-COL-1000-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 250 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 Referendum-COL-1000-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 2500 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 5/250 1/2000 Referendum-COL-1000-CTLFireability-2024-09 53160 m, 10632 m/sec, 800628 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 5/2500 1/5 Referendum-COL-1000-CTLFireability-2024-10 55784 m, -399876 m/sec, 845408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 10/250 1/2000 Referendum-COL-1000-CTLFireability-2024-09 101679 m, 9703 m/sec, 1642033 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 10/227 1/5 Referendum-COL-1000-CTLFireability-2024-10 105902 m, 10023 m/sec, 1714715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 15/250 1/2000 Referendum-COL-1000-CTLFireability-2024-09 148052 m, 9274 m/sec, 2482839 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 15/227 1/5 Referendum-COL-1000-CTLFireability-2024-10 154088 m, 9637 m/sec, 2582116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 20/250 2/2000 Referendum-COL-1000-CTLFireability-2024-09 193513 m, 9092 m/sec, 3318871 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 20/227 2/5 Referendum-COL-1000-CTLFireability-2024-10 200015 m, 9185 m/sec, 3444815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 25/250 2/2000 Referendum-COL-1000-CTLFireability-2024-09 237179 m, 8733 m/sec, 4156796 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 25/227 2/5 Referendum-COL-1000-CTLFireability-2024-10 244602 m, 8917 m/sec, 4309530 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 30/250 2/2000 Referendum-COL-1000-CTLFireability-2024-09 280493 m, 8662 m/sec, 4995109 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 30/227 2/5 Referendum-COL-1000-CTLFireability-2024-10 290647 m, 9209 m/sec, 5171425 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 35/250 2/2000 Referendum-COL-1000-CTLFireability-2024-09 325409 m, 8983 m/sec, 5825302 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 35/227 3/5 Referendum-COL-1000-CTLFireability-2024-10 336327 m, 9136 m/sec, 6027231 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 40/250 3/2000 Referendum-COL-1000-CTLFireability-2024-09 368721 m, 8662 m/sec, 6657094 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 40/227 3/5 Referendum-COL-1000-CTLFireability-2024-10 379608 m, 8656 m/sec, 6882684 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 45/250 3/2000 Referendum-COL-1000-CTLFireability-2024-09 409925 m, 8240 m/sec, 7489574 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 45/227 3/5 Referendum-COL-1000-CTLFireability-2024-10 422652 m, 8608 m/sec, 7736967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 50/250 3/2000 Referendum-COL-1000-CTLFireability-2024-09 451193 m, 8253 m/sec, 8323047 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 50/227 3/5 Referendum-COL-1000-CTLFireability-2024-10 463727 m, 8215 m/sec, 8591842 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 55/250 4/2000 Referendum-COL-1000-CTLFireability-2024-09 490432 m, 7847 m/sec, 9156819 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 55/227 4/5 Referendum-COL-1000-CTLFireability-2024-10 503929 m, 8040 m/sec, 9449667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 60/250 4/2000 Referendum-COL-1000-CTLFireability-2024-09 527528 m, 7419 m/sec, 9991312 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 60/227 4/5 Referendum-COL-1000-CTLFireability-2024-10 546734 m, 8561 m/sec, 10305550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 65/250 4/2000 Referendum-COL-1000-CTLFireability-2024-09 574579 m, 9410 m/sec, 10816300 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 65/227 4/5 Referendum-COL-1000-CTLFireability-2024-10 591903 m, 9033 m/sec, 11157210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 70/250 4/2000 Referendum-COL-1000-CTLFireability-2024-09 618049 m, 8694 m/sec, 11643101 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 70/227 4/5 Referendum-COL-1000-CTLFireability-2024-10 636323 m, 8884 m/sec, 12010726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 75/250 5/2000 Referendum-COL-1000-CTLFireability-2024-09 657565 m, 7903 m/sec, 12469675 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 75/227 5/5 Referendum-COL-1000-CTLFireability-2024-10 678983 m, 8532 m/sec, 12862135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 80/250 5/2000 Referendum-COL-1000-CTLFireability-2024-09 700790 m, 8645 m/sec, 13298773 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 80/227 5/5 Referendum-COL-1000-CTLFireability-2024-10 719986 m, 8200 m/sec, 13715496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 85/250 5/2000 Referendum-COL-1000-CTLFireability-2024-09 740201 m, 7882 m/sec, 14127413 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 85/227 5/5 Referendum-COL-1000-CTLFireability-2024-10 760486 m, 8100 m/sec, 14569161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 90/250 5/2000 Referendum-COL-1000-CTLFireability-2024-09 777422 m, 7444 m/sec, 14954596 t fired, .
[[35mlola[0m][.] 51 CTL EXCL 90/227 5/5 Referendum-COL-1000-CTLFireability-2024-10 799823 m, 7867 m/sec, 15420006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 51 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-10 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 95/250 6/2000 Referendum-COL-1000-CTLFireability-2024-09 818243 m, 8164 m/sec, 15782687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 100/250 6/2000 Referendum-COL-1000-CTLFireability-2024-09 858327 m, 8016 m/sec, 16612671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 105/250 6/2000 Referendum-COL-1000-CTLFireability-2024-09 896954 m, 7725 m/sec, 17440885 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 110/250 6/2000 Referendum-COL-1000-CTLFireability-2024-09 934262 m, 7461 m/sec, 18270125 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 115/250 6/2000 Referendum-COL-1000-CTLFireability-2024-09 971948 m, 7537 m/sec, 19100569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 120/250 7/2000 Referendum-COL-1000-CTLFireability-2024-09 1007935 m, 7197 m/sec, 19930450 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 125/250 7/2000 Referendum-COL-1000-CTLFireability-2024-09 1041842 m, 6781 m/sec, 20762027 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 130/250 7/2000 Referendum-COL-1000-CTLFireability-2024-09 1086147 m, 8861 m/sec, 21589384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 135/250 7/2000 Referendum-COL-1000-CTLFireability-2024-09 1130116 m, 8793 m/sec, 22416945 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 140/250 8/2000 Referendum-COL-1000-CTLFireability-2024-09 1171221 m, 8221 m/sec, 23244964 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 145/250 8/2000 Referendum-COL-1000-CTLFireability-2024-09 1212821 m, 8320 m/sec, 24070817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 150/250 8/2000 Referendum-COL-1000-CTLFireability-2024-09 1252929 m, 8021 m/sec, 24897779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 155/250 8/2000 Referendum-COL-1000-CTLFireability-2024-09 1291277 m, 7669 m/sec, 25724686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 160/250 9/2000 Referendum-COL-1000-CTLFireability-2024-09 1330649 m, 7874 m/sec, 26553722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 165/250 9/2000 Referendum-COL-1000-CTLFireability-2024-09 1371199 m, 8110 m/sec, 27382484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 170/250 9/2000 Referendum-COL-1000-CTLFireability-2024-09 1409860 m, 7732 m/sec, 28209851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 175/250 9/2000 Referendum-COL-1000-CTLFireability-2024-09 1446720 m, 7372 m/sec, 29037988 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 180/250 9/2000 Referendum-COL-1000-CTLFireability-2024-09 1485578 m, 7771 m/sec, 29865901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 185/250 10/2000 Referendum-COL-1000-CTLFireability-2024-09 1521787 m, 7241 m/sec, 30697707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 190/250 10/2000 Referendum-COL-1000-CTLFireability-2024-09 1556473 m, 6937 m/sec, 31528602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 195/250 10/2000 Referendum-COL-1000-CTLFireability-2024-09 1594748 m, 7655 m/sec, 32357951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 200/250 10/2000 Referendum-COL-1000-CTLFireability-2024-09 1634934 m, 8037 m/sec, 33185688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 205/250 10/2000 Referendum-COL-1000-CTLFireability-2024-09 1673936 m, 7800 m/sec, 34014360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 210/250 11/2000 Referendum-COL-1000-CTLFireability-2024-09 1710796 m, 7372 m/sec, 34841684 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 215/250 11/2000 Referendum-COL-1000-CTLFireability-2024-09 1749571 m, 7755 m/sec, 35674857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 220/250 11/2000 Referendum-COL-1000-CTLFireability-2024-09 1785752 m, 7236 m/sec, 36508871 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 225/250 11/2000 Referendum-COL-1000-CTLFireability-2024-09 1820536 m, 6956 m/sec, 37343718 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 230/250 12/2000 Referendum-COL-1000-CTLFireability-2024-09 1857380 m, 7368 m/sec, 38176994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 235/250 12/2000 Referendum-COL-1000-CTLFireability-2024-09 1894422 m, 7408 m/sec, 39010375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 240/250 12/2000 Referendum-COL-1000-CTLFireability-2024-09 1930475 m, 7210 m/sec, 39844602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 245/250 12/2000 Referendum-COL-1000-CTLFireability-2024-09 1964086 m, 6722 m/sec, 40678525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 250/250 12/2000 Referendum-COL-1000-CTLFireability-2024-09 1999651 m, 7113 m/sec, 41512400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 48 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-09 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 3 0 0 4 1 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 35 Referendum-COL-1000-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 249 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 35 Referendum-COL-1000-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 2245 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 5/280 1/5 Referendum-COL-1000-CTLFireability-2024-09 54275 m, -389075 m/sec, 820550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 10/280 1/5 Referendum-COL-1000-CTLFireability-2024-09 103079 m, 9760 m/sec, 1665903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 15/280 1/5 Referendum-COL-1000-CTLFireability-2024-09 149688 m, 9321 m/sec, 2508592 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 20/280 2/5 Referendum-COL-1000-CTLFireability-2024-09 195065 m, 9075 m/sec, 3350489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 25/280 2/5 Referendum-COL-1000-CTLFireability-2024-09 238946 m, 8776 m/sec, 4193397 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 30/280 2/5 Referendum-COL-1000-CTLFireability-2024-09 282962 m, 8803 m/sec, 5034832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 35/280 3/5 Referendum-COL-1000-CTLFireability-2024-09 327574 m, 8922 m/sec, 5872844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 40/280 3/5 Referendum-COL-1000-CTLFireability-2024-09 371476 m, 8780 m/sec, 6711816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 45/280 3/5 Referendum-COL-1000-CTLFireability-2024-09 413309 m, 8366 m/sec, 7551090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 50/280 3/5 Referendum-COL-1000-CTLFireability-2024-09 454361 m, 8210 m/sec, 8391582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 55/280 4/5 Referendum-COL-1000-CTLFireability-2024-09 493869 m, 7901 m/sec, 9233272 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 60/280 4/5 Referendum-COL-1000-CTLFireability-2024-09 532841 m, 7794 m/sec, 10073310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 65/280 4/5 Referendum-COL-1000-CTLFireability-2024-09 579577 m, 9347 m/sec, 10906949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 70/280 4/5 Referendum-COL-1000-CTLFireability-2024-09 622585 m, 8601 m/sec, 11740647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 75/280 5/5 Referendum-COL-1000-CTLFireability-2024-09 663695 m, 8222 m/sec, 12574631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 80/280 5/5 Referendum-COL-1000-CTLFireability-2024-09 705904 m, 8441 m/sec, 13409644 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 85/280 5/5 Referendum-COL-1000-CTLFireability-2024-09 745779 m, 7975 m/sec, 14246260 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 1 0 5 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 CTL EXCL 90/280 5/5 Referendum-COL-1000-CTLFireability-2024-09 782687 m, 7381 m/sec, 15081636 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 48 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-09 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 21 Referendum-COL-1000-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 307 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 5/307 1/2000 Referendum-COL-1000-CTLFireability-2024-07 51144 m, 10228 m/sec, 870834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 10/307 1/2000 Referendum-COL-1000-CTLFireability-2024-07 96646 m, 9100 m/sec, 1744259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 15/307 1/2000 Referendum-COL-1000-CTLFireability-2024-07 139414 m, 8553 m/sec, 2615271 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 20/307 2/2000 Referendum-COL-1000-CTLFireability-2024-07 183326 m, 8782 m/sec, 3483545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 25/307 2/2000 Referendum-COL-1000-CTLFireability-2024-07 224557 m, 8246 m/sec, 4353483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 30/307 2/2000 Referendum-COL-1000-CTLFireability-2024-07 262395 m, 7567 m/sec, 5224651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 35/307 2/2000 Referendum-COL-1000-CTLFireability-2024-07 307511 m, 9023 m/sec, 6090411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 40/307 3/2000 Referendum-COL-1000-CTLFireability-2024-07 348729 m, 8243 m/sec, 6956229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 45/307 3/2000 Referendum-COL-1000-CTLFireability-2024-07 387352 m, 7724 m/sec, 7822998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 50/307 3/2000 Referendum-COL-1000-CTLFireability-2024-07 427092 m, 7948 m/sec, 8688209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 55/307 3/2000 Referendum-COL-1000-CTLFireability-2024-07 465532 m, 7688 m/sec, 9556655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 60/307 4/2000 Referendum-COL-1000-CTLFireability-2024-07 502536 m, 7400 m/sec, 10423676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 65/307 4/2000 Referendum-COL-1000-CTLFireability-2024-07 540787 m, 7650 m/sec, 11288202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 70/307 4/2000 Referendum-COL-1000-CTLFireability-2024-07 583402 m, 8523 m/sec, 12150376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 75/307 4/2000 Referendum-COL-1000-CTLFireability-2024-07 623573 m, 8034 m/sec, 13011688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 80/307 5/2000 Referendum-COL-1000-CTLFireability-2024-07 662282 m, 7741 m/sec, 13873367 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 85/307 5/2000 Referendum-COL-1000-CTLFireability-2024-07 702305 m, 8004 m/sec, 14735204 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 90/307 5/2000 Referendum-COL-1000-CTLFireability-2024-07 739747 m, 7488 m/sec, 15597593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 95/307 5/2000 Referendum-COL-1000-CTLFireability-2024-07 775462 m, 7143 m/sec, 16459743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 100/307 5/2000 Referendum-COL-1000-CTLFireability-2024-07 814010 m, 7709 m/sec, 17321994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 105/307 6/2000 Referendum-COL-1000-CTLFireability-2024-07 851583 m, 7514 m/sec, 18183558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 110/307 6/2000 Referendum-COL-1000-CTLFireability-2024-07 889027 m, 7488 m/sec, 19046153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 115/307 6/2000 Referendum-COL-1000-CTLFireability-2024-07 924108 m, 7016 m/sec, 19907586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 120/307 6/2000 Referendum-COL-1000-CTLFireability-2024-07 960947 m, 7367 m/sec, 20770136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 125/307 7/2000 Referendum-COL-1000-CTLFireability-2024-07 995489 m, 6908 m/sec, 21632393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 130/307 7/2000 Referendum-COL-1000-CTLFireability-2024-07 1028941 m, 6690 m/sec, 22493821 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 135/307 7/2000 Referendum-COL-1000-CTLFireability-2024-07 1065333 m, 7278 m/sec, 23352306 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 140/307 7/2000 Referendum-COL-1000-CTLFireability-2024-07 1107766 m, 8486 m/sec, 24210577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 145/307 7/2000 Referendum-COL-1000-CTLFireability-2024-07 1147762 m, 7999 m/sec, 25067361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1595 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 150/307 8/2000 Referendum-COL-1000-CTLFireability-2024-07 1186177 m, 7683 m/sec, 25924022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1600 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 155/307 8/2000 Referendum-COL-1000-CTLFireability-2024-07 1226003 m, 7965 m/sec, 26780601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1605 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 160/307 8/2000 Referendum-COL-1000-CTLFireability-2024-07 1263240 m, 7447 m/sec, 27639374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1610 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 165/307 8/2000 Referendum-COL-1000-CTLFireability-2024-07 1298901 m, 7132 m/sec, 28497146 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1615 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 170/307 9/2000 Referendum-COL-1000-CTLFireability-2024-07 1337110 m, 7641 m/sec, 29354501 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1620 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 175/307 9/2000 Referendum-COL-1000-CTLFireability-2024-07 1374668 m, 7511 m/sec, 30211037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1625 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 180/307 9/2000 Referendum-COL-1000-CTLFireability-2024-07 1411717 m, 7409 m/sec, 31069022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1630 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 185/307 9/2000 Referendum-COL-1000-CTLFireability-2024-07 1446455 m, 6947 m/sec, 31925424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1635 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 190/307 9/2000 Referendum-COL-1000-CTLFireability-2024-07 1483298 m, 7368 m/sec, 32783395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1640 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 195/307 10/2000 Referendum-COL-1000-CTLFireability-2024-07 1517760 m, 6892 m/sec, 33642181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 200/307 10/2000 Referendum-COL-1000-CTLFireability-2024-07 1551304 m, 6708 m/sec, 34500943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1650 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 205/307 10/2000 Referendum-COL-1000-CTLFireability-2024-07 1585710 m, 6881 m/sec, 35357666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1655 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 210/307 10/2000 Referendum-COL-1000-CTLFireability-2024-07 1624795 m, 7817 m/sec, 36215720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1660 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 215/307 10/2000 Referendum-COL-1000-CTLFireability-2024-07 1662085 m, 7458 m/sec, 37073253 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1665 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 220/307 11/2000 Referendum-COL-1000-CTLFireability-2024-07 1697059 m, 6994 m/sec, 37930913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1670 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 225/307 11/2000 Referendum-COL-1000-CTLFireability-2024-07 1733484 m, 7285 m/sec, 38788839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1675 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 230/307 11/2000 Referendum-COL-1000-CTLFireability-2024-07 1768082 m, 6919 m/sec, 39648551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1680 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 235/307 11/2000 Referendum-COL-1000-CTLFireability-2024-07 1802291 m, 6841 m/sec, 40508606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1685 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 240/307 11/2000 Referendum-COL-1000-CTLFireability-2024-07 1834282 m, 6398 m/sec, 41367651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1690 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 245/307 12/2000 Referendum-COL-1000-CTLFireability-2024-07 1871223 m, 7388 m/sec, 42226748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1695 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 250/307 12/2000 Referendum-COL-1000-CTLFireability-2024-07 1905620 m, 6879 m/sec, 43084487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1700 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 255/307 12/2000 Referendum-COL-1000-CTLFireability-2024-07 1939720 m, 6820 m/sec, 43943842 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1705 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 260/307 12/2000 Referendum-COL-1000-CTLFireability-2024-07 1971818 m, 6419 m/sec, 44802329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1710 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 265/307 12/2000 Referendum-COL-1000-CTLFireability-2024-07 2005821 m, 6800 m/sec, 45662647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1715 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 270/307 13/2000 Referendum-COL-1000-CTLFireability-2024-07 2037620 m, 6359 m/sec, 46522493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1720 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 275/307 13/2000 Referendum-COL-1000-CTLFireability-2024-07 2069055 m, 6287 m/sec, 47381464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1725 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 280/307 13/2000 Referendum-COL-1000-CTLFireability-2024-07 2098217 m, 5832 m/sec, 48238170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1730 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 285/307 13/2000 Referendum-COL-1000-CTLFireability-2024-07 2142998 m, 8956 m/sec, 49092727 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1735 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 290/307 13/2000 Referendum-COL-1000-CTLFireability-2024-07 2183610 m, 8122 m/sec, 49945140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1740 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 295/307 14/2000 Referendum-COL-1000-CTLFireability-2024-07 2221608 m, 7599 m/sec, 50797428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1745 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 300/307 14/2000 Referendum-COL-1000-CTLFireability-2024-07 2260889 m, 7856 m/sec, 51649641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1750 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 305/307 14/2000 Referendum-COL-1000-CTLFireability-2024-07 2298397 m, 7501 m/sec, 52503207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1755 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 24 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-07 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 1 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1760 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 Referendum-COL-1000-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 306 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 21 Referendum-COL-1000-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 1840 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 5/306 1/2000 Referendum-COL-1000-CTLFireability-2024-06 56501 m, 11300 m/sec, 858358 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 5/1840 1/5 Referendum-COL-1000-CTLFireability-2024-07 50569 m, -449565 m/sec, 861073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1765 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 10/306 1/2000 Referendum-COL-1000-CTLFireability-2024-06 106603 m, 10020 m/sec, 1727808 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 10/262 1/5 Referendum-COL-1000-CTLFireability-2024-07 96134 m, 9113 m/sec, 1733501 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1770 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 15/306 1/2000 Referendum-COL-1000-CTLFireability-2024-06 154836 m, 9646 m/sec, 2595648 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 15/262 1/5 Referendum-COL-1000-CTLFireability-2024-07 138911 m, 8555 m/sec, 2605743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1775 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 20/306 2/2000 Referendum-COL-1000-CTLFireability-2024-06 200950 m, 9222 m/sec, 3460434 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 20/262 2/5 Referendum-COL-1000-CTLFireability-2024-07 182919 m, 8801 m/sec, 3474974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1780 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 25/306 2/2000 Referendum-COL-1000-CTLFireability-2024-06 245480 m, 8906 m/sec, 4328668 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 25/262 2/5 Referendum-COL-1000-CTLFireability-2024-07 224120 m, 8240 m/sec, 4344197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1785 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 30/306 2/2000 Referendum-COL-1000-CTLFireability-2024-06 291659 m, 9235 m/sec, 5191412 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 30/262 2/5 Referendum-COL-1000-CTLFireability-2024-07 261952 m, 7566 m/sec, 5212678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1790 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 35/306 3/2000 Referendum-COL-1000-CTLFireability-2024-06 337889 m, 9246 m/sec, 6054923 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 35/262 2/5 Referendum-COL-1000-CTLFireability-2024-07 306924 m, 8994 m/sec, 6078101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1795 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 40/306 3/2000 Referendum-COL-1000-CTLFireability-2024-06 380860 m, 8594 m/sec, 6908145 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 40/262 3/5 Referendum-COL-1000-CTLFireability-2024-07 347655 m, 8146 m/sec, 6933579 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1800 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 45/306 3/2000 Referendum-COL-1000-CTLFireability-2024-06 423758 m, 8579 m/sec, 7759660 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 45/262 3/5 Referendum-COL-1000-CTLFireability-2024-07 385808 m, 7630 m/sec, 7787746 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1805 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 50/306 3/2000 Referendum-COL-1000-CTLFireability-2024-06 465007 m, 8249 m/sec, 8615312 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 50/262 3/5 Referendum-COL-1000-CTLFireability-2024-07 425317 m, 7901 m/sec, 8644025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1810 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 55/306 4/2000 Referendum-COL-1000-CTLFireability-2024-06 504933 m, 7985 m/sec, 9473553 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 55/262 3/5 Referendum-COL-1000-CTLFireability-2024-07 462988 m, 7534 m/sec, 9502869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1815 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 60/306 4/2000 Referendum-COL-1000-CTLFireability-2024-06 548295 m, 8672 m/sec, 10333198 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 60/262 4/5 Referendum-COL-1000-CTLFireability-2024-07 500177 m, 7437 m/sec, 10368101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1820 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 65/306 4/2000 Referendum-COL-1000-CTLFireability-2024-06 593867 m, 9114 m/sec, 11188866 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 65/262 4/5 Referendum-COL-1000-CTLFireability-2024-07 537749 m, 7514 m/sec, 11228769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1825 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 70/306 4/2000 Referendum-COL-1000-CTLFireability-2024-06 638069 m, 8840 m/sec, 12048203 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 70/262 4/5 Referendum-COL-1000-CTLFireability-2024-07 580717 m, 8593 m/sec, 12090922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1830 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 75/306 5/2000 Referendum-COL-1000-CTLFireability-2024-06 681047 m, 8595 m/sec, 12905208 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 75/262 4/5 Referendum-COL-1000-CTLFireability-2024-07 621125 m, 8081 m/sec, 12950222 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1835 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 80/306 5/2000 Referendum-COL-1000-CTLFireability-2024-06 721915 m, 8173 m/sec, 13763863 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 80/262 5/5 Referendum-COL-1000-CTLFireability-2024-07 658894 m, 7553 m/sec, 13808707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1840 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 85/306 5/2000 Referendum-COL-1000-CTLFireability-2024-06 762732 m, 8163 m/sec, 14620708 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 85/262 5/5 Referendum-COL-1000-CTLFireability-2024-07 699437 m, 8108 m/sec, 14670116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1845 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 90/306 5/2000 Referendum-COL-1000-CTLFireability-2024-06 802866 m, 8026 m/sec, 15479294 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 90/262 5/5 Referendum-COL-1000-CTLFireability-2024-07 736852 m, 7483 m/sec, 15531087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1850 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 95/306 6/2000 Referendum-COL-1000-CTLFireability-2024-06 845379 m, 8502 m/sec, 16339275 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 95/262 5/5 Referendum-COL-1000-CTLFireability-2024-07 772711 m, 7171 m/sec, 16391680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1855 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 1 0 4 0 0 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 100/306 6/2000 Referendum-COL-1000-CTLFireability-2024-06 885519 m, 8028 m/sec, 17198428 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 100/262 5/5 Referendum-COL-1000-CTLFireability-2024-07 810875 m, 7632 m/sec, 17252809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1860 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 24 (type EXCL) for Referendum-COL-1000-CTLFireability-2024-07 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 105/306 6/2000 Referendum-COL-1000-CTLFireability-2024-06 924745 m, 7845 m/sec, 18072307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1865 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 110/306 6/2000 Referendum-COL-1000-CTLFireability-2024-06 965363 m, 8123 m/sec, 18949168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1870 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 115/306 7/2000 Referendum-COL-1000-CTLFireability-2024-06 1003302 m, 7587 m/sec, 19821157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1875 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 120/306 7/2000 Referendum-COL-1000-CTLFireability-2024-06 1038733 m, 7086 m/sec, 20680094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1880 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 125/306 7/2000 Referendum-COL-1000-CTLFireability-2024-06 1082778 m, 8809 m/sec, 21535143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1885 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 130/306 7/2000 Referendum-COL-1000-CTLFireability-2024-06 1128786 m, 9201 m/sec, 22390418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1890 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 135/306 8/2000 Referendum-COL-1000-CTLFireability-2024-06 1171156 m, 8474 m/sec, 23243612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1895 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 140/306 8/2000 Referendum-COL-1000-CTLFireability-2024-06 1214089 m, 8586 m/sec, 24095749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1900 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 145/306 8/2000 Referendum-COL-1000-CTLFireability-2024-06 1255593 m, 8300 m/sec, 24951262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1905 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 150/306 8/2000 Referendum-COL-1000-CTLFireability-2024-06 1294739 m, 7829 m/sec, 25806388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1910 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-15: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-05: SP ACTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-07: DISJ 0 0 0 0 4 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-09: DISJ 0 1 0 0 5 0 1 1
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Referendum-COL-1000-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 155/306 9/2000 Referendum-COL-1000-CTLFireability-2024-06 1336067 m, 8265 m/sec, 26660666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1915 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-04: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mReferendum-COL-1000-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mReferendum-COL-1000-CTLFireability-2024-14: CTL true skeleton: CTL model checker[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Referendum-COL-1000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Referendum-COL-1000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662340700570"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Referendum-COL-1000.tgz
mv Referendum-COL-1000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;