About the Execution of LoLA for Railroad-PT-010
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1038.979 | 74504.00 | 75183.00 | 394.30 | FFFFFFTFFFFFTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662340600484.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Railroad-PT-010, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662340600484
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 544K
-rw-r--r-- 1 mcc users 7.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 23 07:46 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:46 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Apr 23 07:46 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 23 07:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 12 14:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 135K Apr 12 14:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Apr 12 14:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Apr 12 14:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:46 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:46 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 82K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Railroad-PT-010-LTLFireability-00
FORMULA_NAME Railroad-PT-010-LTLFireability-01
FORMULA_NAME Railroad-PT-010-LTLFireability-02
FORMULA_NAME Railroad-PT-010-LTLFireability-03
FORMULA_NAME Railroad-PT-010-LTLFireability-04
FORMULA_NAME Railroad-PT-010-LTLFireability-05
FORMULA_NAME Railroad-PT-010-LTLFireability-06
FORMULA_NAME Railroad-PT-010-LTLFireability-07
FORMULA_NAME Railroad-PT-010-LTLFireability-08
FORMULA_NAME Railroad-PT-010-LTLFireability-09
FORMULA_NAME Railroad-PT-010-LTLFireability-10
FORMULA_NAME Railroad-PT-010-LTLFireability-11
FORMULA_NAME Railroad-PT-010-LTLFireability-12
FORMULA_NAME Railroad-PT-010-LTLFireability-13
FORMULA_NAME Railroad-PT-010-LTLFireability-14
FORMULA_NAME Railroad-PT-010-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717331562187
FORMULA Railroad-PT-010-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-02: CONJ false findpath[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mRailroad-PT-010-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mRailroad-PT-010-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 74 secs. Pages in use: 27
BK_STOP 1717331636691
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 10 transitions removed,31 places removed
[[35mlola[0m][I] LAUNCH task # 3 (type CNST) for 0 Railroad-PT-010-LTLFireability-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 3 (type CNST) for Railroad-PT-010-LTLFireability-00
[[35mlola[0m][I] result : false
[*** LOG ERROR #0001 ***] [2024-06-02 12:32:42] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 Railroad-PT-010-LTLFireability-06
[[35mlola[0m][I] time limit : 120 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for Railroad-PT-010-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 51
[[35mlola[0m][I] fired transitions : 60
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 31 Railroad-PT-010-LTLFireability-05
[[35mlola[0m][I] time limit : 124 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for Railroad-PT-010-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 10
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 59 Railroad-PT-010-LTLFireability-13
[[35mlola[0m][I] time limit : 133 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for Railroad-PT-010-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 56 Railroad-PT-010-LTLFireability-12
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 73 (type FNDP) for 10 Railroad-PT-010-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 10 Railroad-PT-010-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type FNDP) for Railroad-PT-010-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 74 (type EQUN) for Railroad-PT-010-LTLFireability-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for Railroad-PT-010-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRailroad-PT-010-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mRailroad-PT-010-LTLFireability-02: CONJ false findpath[0m
[[35mlola[0m][.] [1m[32mRailroad-PT-010-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mRailroad-PT-010-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-05: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 LTL EXCL 5/300 8/2000 Railroad-PT-010-LTLFireability-12 1120964 m, 224192 m/sec, 4993967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRailroad-PT-010-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mRailroad-PT-010-LTLFireability-02: CONJ false findpath[0m
[[35mlola[0m][.] [1m[32mRailroad-PT-010-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mRailroad-PT-010-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-05: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 LTL EXCL 10/300 13/2000 Railroad-PT-010-LTLFireability-12 1959104 m, 167628 m/sec, 9593436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mRailroad-PT-010-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mRailroad-PT-010-LTLFireability-02: CONJ false findpath[0m
[[35mlola[0m][.] [1m[32mRailroad-PT-010-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mRailroad-PT-010-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-05: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 LTL EXCL 15/300 14/2000 Railroad-PT-010-LTLFireability-12 2038144 m, 15808 m/sec, 13972604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for Railroad-PT-010-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2038187
[[35mlola[0m][I] fired transitions : 16324621
[[35mlola[0m][I] time used : 18
[[35mlola[0m][I] memory pages used : 14
[[35mlola[0m][I] LAUNCH task # 70 (type EXCL) for 69 Railroad-PT-010-LTLFireability-15
[[35mlola[0m][I] time limit : 325 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for Railroad-PT-010-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 66 Railroad-PT-010-LTLFireability-14
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for Railroad-PT-010-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 14
[[35mlola[0m][I] fired transitions : 14
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 Railroad-PT-010-LTLFireability-11
[[35mlola[0m][I] time limit : 398 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for Railroad-PT-010-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 Railroad-PT-010-LTLFireability-10
[[35mlola[0m][I] time limit : 447 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for Railroad-PT-010-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1131
[[35mlola[0m][I] fired transitions : 2681
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 Railroad-PT-010-LTLFireability-09
[[35mlola[0m][I] time limit : 511 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for Railroad-PT-010-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 20580
[[35mlola[0m][I] fired transitions : 67791
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 Railroad-PT-010-LTLFireability-07
[[35mlola[0m][I] time limit : 597 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for Railroad-PT-010-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 13
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][.] 26 LTL EXCL 2/716 3/2000 Railroad-PT-010-LTLFireability-03 457952 m, 91590 m/sec, 3112277 t fired, .
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[[35mlola[0m][.] 26 LTL EXCL 7/716 8/2000 Railroad-PT-010-LTLFireability-03 1229369 m, 154283 m/sec, 9326188 t fired, .
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[[35mlola[0m][.] 26 LTL EXCL 12/716 13/2000 Railroad-PT-010-LTLFireability-03 1918375 m, 137801 m/sec, 15274668 t fired, .
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[[35mlola[0m][.] 26 LTL EXCL 17/716 17/2000 Railroad-PT-010-LTLFireability-03 2549102 m, 126145 m/sec, 21032252 t fired, .
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[[35mlola[0m][.] 26 LTL EXCL 22/716 21/2000 Railroad-PT-010-LTLFireability-03 3131379 m, 116455 m/sec, 26715100 t fired, .
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[[35mlola[0m][.] 26 LTL EXCL 27/716 24/2000 Railroad-PT-010-LTLFireability-03 3669569 m, 107638 m/sec, 32367535 t fired, .
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[[35mlola[0m][.] Railroad-PT-010-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 26 LTL EXCL 47/716 27/2000 Railroad-PT-010-LTLFireability-03 4136710 m, 22 m/sec, 54403262 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] 26 LTL EXCL 52/716 27/2000 Railroad-PT-010-LTLFireability-03 4137232 m, 104 m/sec, 59909750 t fired, .
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[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 Railroad-PT-010-LTLFireability-01
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[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for Railroad-PT-010-LTLFireability-01
[[35mlola[0m][I] result : false
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[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 Railroad-PT-010-LTLFireability-08
[[35mlola[0m][I] time limit : 1175 sec
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[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for Railroad-PT-010-LTLFireability-08
[[35mlola[0m][I] result : false
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for Railroad-PT-010-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 Railroad-PT-010-LTLFireability-04
[[35mlola[0m][I] time limit : 3526 sec
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[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for Railroad-PT-010-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5651
[[35mlola[0m][I] fired transitions : 16848
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Railroad-PT-010"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Railroad-PT-010, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662340600484"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Railroad-PT-010.tgz
mv Railroad-PT-010 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;