About the Execution of LoLA for Railroad-PT-010
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1618.684 | 188993.00 | 319593.00 | 358.00 | TFTTTTFFTTTTTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662340600481.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Railroad-PT-010, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662340600481
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 544K
-rw-r--r-- 1 mcc users 7.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 23 07:46 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:46 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Apr 23 07:46 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 23 07:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 12 14:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 135K Apr 12 14:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Apr 12 14:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Apr 12 14:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:46 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 23 07:46 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 82K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-00
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-01
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-02
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-03
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-04
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-05
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-06
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-07
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-08
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-09
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-10
FORMULA_NAME Railroad-PT-010-CTLCardinality-2024-11
FORMULA_NAME Railroad-PT-010-CTLCardinality-2023-12
FORMULA_NAME Railroad-PT-010-CTLCardinality-2023-13
FORMULA_NAME Railroad-PT-010-CTLCardinality-2023-14
FORMULA_NAME Railroad-PT-010-CTLCardinality-2023-15
=== Now, execution of the tool begins
BK_START 1717331516238
FORMULA Railroad-PT-010-CTLCardinality-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Railroad-PT-010-CTLCardinality-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mRailroad-PT-010-CTLCardinality-2024-00: CTL true CTL model checker[0m
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[[35mlola[0m] [1m[32mRailroad-PT-010-CTLCardinality-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mRailroad-PT-010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mRailroad-PT-010-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mRailroad-PT-010-CTLCardinality-2024-08: CONJ true CONJ[0m
[[35mlola[0m] [1m[32mRailroad-PT-010-CTLCardinality-2024-09: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[32mRailroad-PT-010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[32mRailroad-PT-010-CTLCardinality-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mRailroad-PT-010-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-CTLCardinality-2023-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-CTLCardinality-2023-14: EFEG false state space /EFEG[0m
[[35mlola[0m] [1m[31mRailroad-PT-010-CTLCardinality-2023-15: LTL/CTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 189 secs. Pages in use: 9
BK_STOP 1717331705231
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] LAUNCH task # 7 (type CNST) for 6 Railroad-PT-010-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 7 (type CNST) for Railroad-PT-010-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 10 transitions removed,31 places removed
[[35mlola[0m][I] LAUNCH task # 32 (type CNST) for 31 Railroad-PT-010-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 32 (type CNST) for Railroad-PT-010-CTLCardinality-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 Railroad-PT-010-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 35 (type CNST) for 34 Railroad-PT-010-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for Railroad-PT-010-CTLCardinality-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 35 (type CNST) for Railroad-PT-010-CTLCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 16 (type CNST) for 15 Railroad-PT-010-CTLCardinality-2024-05
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 16 (type CNST) for Railroad-PT-010-CTLCardinality-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 Railroad-PT-010-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 294 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for Railroad-PT-010-CTLCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 83
[[35mlola[0m][I] fired transitions : 117
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 Railroad-PT-010-CTLCardinality-2024-06
[[35mlola[0m][I] time limit : 321 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 55 (type EQUN) for 46 Railroad-PT-010-CTLCardinality-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 46 Railroad-PT-010-CTLCardinality-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type EQUN) for Railroad-PT-010-CTLCardinality-2023-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.] [1m[32mRailroad-PT-010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-14: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 5/321 4/2000 Railroad-PT-010-CTLCardinality-2024-06 946348 m, 189269 m/sec, 5639146 t fired, .
[[35mlola[0m][.] 57 EF STEQ 5/3539 0/5 Railroad-PT-010-CTLCardinality-2023-14 sara not yet started (preprocessing).
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[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-14: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 10/321 7/2000 Railroad-PT-010-CTLCardinality-2024-06 1662356 m, 143201 m/sec, 10506486 t fired, .
[[35mlola[0m][.] 57 EF STEQ 10/3539 0/5 Railroad-PT-010-CTLCardinality-2023-14 sara not yet started (preprocessing).
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[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-08: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-14: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 15/321 9/2000 Railroad-PT-010-CTLCardinality-2024-06 2037791 m, 75087 m/sec, 15139216 t fired, .
[[35mlola[0m][.] 57 EF STEQ 15/3539 0/5 Railroad-PT-010-CTLCardinality-2023-14 sara not yet started (preprocessing).
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[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-14: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-15: LTL/CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 19 CTL EXCL 20/321 9/2000 Railroad-PT-010-CTLCardinality-2024-06 2038166 m, 75 m/sec, 19419440 t fired, .
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[[35mlola[0m][I] markings : 2038166
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[[35mlola[0m][I] time used : 20
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[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 Railroad-PT-010-CTLCardinality-2023-15
[[35mlola[0m][I] time limit : 351 sec
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[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for Railroad-PT-010-CTLCardinality-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 Railroad-PT-010-CTLCardinality-2023-13
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[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for Railroad-PT-010-CTLCardinality-2023-13
[[35mlola[0m][I] result : false
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[[35mlola[0m][I] fired transitions : 1672248
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 Railroad-PT-010-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 439 sec
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[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for Railroad-PT-010-CTLCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 24 Railroad-PT-010-CTLCardinality-2024-08
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[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-08: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-14: EFEG 0 1 1 0 2 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 4/502 4/2000 Railroad-PT-010-CTLCardinality-2024-08 823221 m, 164644 m/sec, 3545159 t fired, .
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[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-08: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-14: EFEG 0 1 1 0 2 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 9/502 7/2000 Railroad-PT-010-CTLCardinality-2024-08 1658420 m, 167039 m/sec, 7813329 t fired, .
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[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-08: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-14: EFEG 0 1 1 0 2 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 14/502 9/2000 Railroad-PT-010-CTLCardinality-2024-08 2037938 m, 75903 m/sec, 12291897 t fired, .
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[[35mlola[0m][I] markings : 2038166
[[35mlola[0m][I] fired transitions : 16324600
[[35mlola[0m][I] time used : 18
[[35mlola[0m][I] memory pages used : 9
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 24 Railroad-PT-010-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 583 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-08: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-14: EFEG 0 1 1 0 2 0 0 0
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[[35mlola[0m][.] 27 CTL EXCL 1/583 1/2000 Railroad-PT-010-CTLCardinality-2024-08 69491 m, 13898 m/sec, 358548 t fired, .
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[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2024-08: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Railroad-PT-010-CTLCardinality-2023-14: EFEG 0 1 1 0 2 0 0 0
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[[35mlola[0m][.] 27 CTL EXCL 21/583 9/2000 Railroad-PT-010-CTLCardinality-2024-08 2038147 m, 3691 m/sec, 17679727 t fired, .
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2038166
[[35mlola[0m][I] fired transitions : 19653812
[[35mlola[0m][I] time used : 23
[[35mlola[0m][I] memory pages used : 9
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 Railroad-PT-010-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 695 sec
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[[35mlola[0m][.] 22 CTL EXCL 3/695 3/2000 Railroad-PT-010-CTLCardinality-2024-07 529559 m, 105911 m/sec, 2769971 t fired, .
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[[35mlola[0m][I] markings : 2038166
[[35mlola[0m][I] fired transitions : 18661630
[[35mlola[0m][I] time used : 22
[[35mlola[0m][I] memory pages used : 9
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 Railroad-PT-010-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 863 sec
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2038166
[[35mlola[0m][I] fired transitions : 34687366
[[35mlola[0m][I] time used : 36
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[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 46 Railroad-PT-010-CTLCardinality-2023-14
[[35mlola[0m][I] time limit : 1139 sec
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[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for Railroad-PT-010-CTLCardinality-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 117137
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[[35mlola[0m][I] time used : 2
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[[35mlola[0m][W] CANCELED task # 57 (type EQUN) for Railroad-PT-010-CTLCardinality-2023-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 Railroad-PT-010-CTLCardinality-2023-12
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[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for Railroad-PT-010-CTLCardinality-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 155991
[[35mlola[0m][I] fired transitions : 1377498
[[35mlola[0m][I] time used : 1
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[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 Railroad-PT-010-CTLCardinality-2024-04
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[[35mlola[0m][.] 13 CTL EXCL 2/3416 2/2000 Railroad-PT-010-CTLCardinality-2024-04 343435 m, 68687 m/sec, 2949010 t fired, .
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 368127
[[35mlola[0m][I] fired transitions : 6205701
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Railroad-PT-010"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Railroad-PT-010, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662340600481"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Railroad-PT-010.tgz
mv Railroad-PT-010 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;