MCC'2024- Execution of r313-tall-171662340500434

About the Execution of LoLA for Raft-PT-06

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16208.020	256078.00	241984.00	1478.10	???????????T????	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r313-tall-171662340500434.qcow2',
Waiting for the VM to be ready (probing ssh)
....................
=================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Raft-PT-06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662340500434
=======================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 612K
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLCardinality
-rw-r--r-- 1 mcc users 55K May 14 13:22 CTLCardinality
-rw-r--r-- 1 mcc users 6.0K May 14 13:22 CTLFireability
-rw-r--r-- 1 mcc users 59K May 14 13:22 CTLFireability
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropert
-rw-r--r-- 1 mcc users 6.2K May 18 16:43 GenericPropert
-rw-r--r-- 1 mcc users 3.1K Apr 23 07:46 LTLCardinality
-rw-r--r-- 1 mcc users 21K Apr 23 07:46 LTLCardinality
-rw-r--r-- 1 mcc users 2.2K Apr 23 07:46 LTLFireability
-rw-r--r-- 1 mcc users 18K Apr 23 07:46 LTLFireability
-rw-r--r-- 1 mcc users 14K Apr 11 17:50 ReachabilityCa
-rw-r--r-- 1 mcc users 164K Apr 11 17:50 ReachabilityCa
-rw-r--r-- 1 mcc users 12K Apr 11 17:46 ReachabilityFi
-rw-r--r-- 1 mcc users 108K Apr 11 17:46 ReachabilityFi
-rw-r--r-- 1 mcc users 1.5K Apr 23 07:46 UpperBounds.tx
-rw-r--r-- 1 mcc users 3.5K Apr 23 07:46 UpperBounds.xm
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 89K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME Raft-PT-06-CTLFireability-2024-00
FORMULA_NAME Raft-PT-06-CTLFireability-2024-01
FORMULA_NAME Raft-PT-06-CTLFireability-2024-02
FORMULA_NAME Raft-PT-06-CTLFireability-2024-03
FORMULA_NAME Raft-PT-06-CTLFireability-2024-04
FORMULA_NAME Raft-PT-06-CTLFireability-2024-05
FORMULA_NAME Raft-PT-06-CTLFireability-2024-06
FORMULA_NAME Raft-PT-06-CTLFireability-2024-07
FORMULA_NAME Raft-PT-06-CTLFireability-2024-08
FORMULA_NAME Raft-PT-06-CTLFireability-2024-09
FORMULA_NAME Raft-PT-06-CTLFireability-2024-10
FORMULA_NAME Raft-PT-06-CTLFireability-2024-11
FORMULA_NAME Raft-PT-06-CTLFireability-2023-12
FORMULA_NAME Raft-PT-06-CTLFireability-2023-13
FORMULA_NAME Raft-PT-06-CTLFireability-2023-14
FORMULA_NAME Raft-PT-06-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717329789224

FORMULA Raft-PT-06-CTLFireability-2024-11

BK_STOP 1717330045302

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmln
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlfo
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0
[[35mlola[0m][I] LAUNCH task # 42 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 42 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 59 (type SKEL/EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 58 (type
[[35mlola[0m][W] CANCELED task # 59 (type
[[35mlola[0m][I] FINISHED task # 58 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] FINISHED task # 59 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL)
[[35mlola[0m][I] time limit : 180 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 69 (type FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][W] CANCELED task # 69 (type
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] FINISHED task # 66 (type
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 68 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mRaft-PT-06-CTLFireability-2024-11:
[[35mlola[0m][.]
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-10:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-12:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-13:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-14:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-15:
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[[35mlola[0m][.] 10 CTL EXCL 5/240
[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mRaft-PT-06-CTLFireability-2024-11:
[[35mlola[0m][.]
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-00:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-02:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-07:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-08:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-09:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-10:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-12:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-13:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-14:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-15:
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[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mRaft-PT-06-CTLFireability-2024-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-07:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-10:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-12:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-13:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-14:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-15:
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[[35mlola[0m][.] 10 CTL EXCL 15/240
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mRaft-PT-06-CTLFireability-2024-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-00:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-02:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-04:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-09:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-10:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-12:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-13:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-14:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-15:
[[35mlola[0m][.]
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[[35mlola[0m][.] 10 CTL EXCL 20/240
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mRaft-PT-06-CTLFireability-2024-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-00:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-01:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-02:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-06:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-09:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-10:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-12:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-13:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-14:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-15:
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mRaft-PT-06-CTLFireability-2024-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-00:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-01:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-02:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-03:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-06:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-07:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-08:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-09:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-10:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-12:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-13:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-14:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-15:
[[35mlola[0m][.]
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[[35mlola[0m][.] 10 CTL EXCL 30/240
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs.
[[35mlola[0m][.] # running tasks: 1 of 4.
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mRaft-PT-06-CTLFireability-2024-11:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-00:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-09:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-10:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-12:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-13:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-14:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-15:
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 1 of 4.
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[[35mlola[0m][.] [1m[32mRaft-PT-06-CTLFireability-2024-11:
[[35mlola[0m][.]
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-12:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-13:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-14:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-15:
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[[35mlola[0m][.] [1m[32mRaft-PT-06-CTLFireability-2024-11:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2024-00:
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[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-12:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-13:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-14:
[[35mlola[0m][.] Raft-PT-06-CTLFireability-2023-15:
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Pages in use: 228 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 235/2000 Raft-PT-06-CTLFireability-2024-03 55637813 m, 355033 m/sec, 101470218 t fired, . Pages in use: 235 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 243/2000 Raft-PT-06-CTLFireability-2024-03 57413527 m, 355142 m/sec, 104744113 t fired, . Pages in use: 243 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 250/2000 Raft-PT-06-CTLFireability-2024-03 59182459 m, 353786 m/sec, 108009964 t fired, . Pages in use: 250 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 258/2000 Raft-PT-06-CTLFireability-2024-03 60946862 m, 352880 m/sec, 111264378 t fired, . Pages in use: 258 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 265/2000 Raft-PT-06-CTLFireability-2024-03 62618713 m, 334370 m/sec, 114372005 t fired, . Pages in use: 265 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 273/2000 Raft-PT-06-CTLFireability-2024-03 64587830 m, 393823 m/sec, 117980394 t fired, . Pages in use: 273 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 281/2000 Raft-PT-06-CTLFireability-2024-03 66400564 m, 362546 m/sec, 121322674 t fired, . Pages in use: 281 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 288/2000 Raft-PT-06-CTLFireability-2024-03 68274008 m, 374688 m/sec, 124772559 t fired, . Pages in use: 288 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 296/2000 Raft-PT-06-CTLFireability-2024-03 70156314 m, 376461 m/sec, 128249913 t fired, . Pages in use: 296 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 304/2000 Raft-PT-06-CTLFireability-2024-03 71957205 m, 360178 m/sec, 131578392 t fired, . Pages in use: 304 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 311/2000 Raft-PT-06-CTLFireability-2024-03 73733334 m, 355225 m/sec, 134865220 t fired, . Pages in use: 311 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 319/2000 Raft-PT-06-CTLFireability-2024-03 75476931 m, 348719 m/sec, 138111515 t fired, . Pages in use: 319 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 326/2000 Raft-PT-06-CTLFireability-2024-03 77225700 m, 349753 m/sec, 141345812 t fired, . Pages in use: 326 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 334/2000 Raft-PT-06-CTLFireability-2024-03 79031440 m, 361148 m/sec, 144687189 t fired, . Pages in use: 334 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 342/2000 Raft-PT-06-CTLFireability-2024-03 81016413 m, 396994 m/sec, 148317486 t fired, . Pages in use: 342 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 351/2000 Raft-PT-06-CTLFireability-2024-03 83058395 m, 408396 m/sec, 152018909 t fired, . Pages in use: 351 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 359/2000 Raft-PT-06-CTLFireability-2024-03 85068878 m, 402096 m/sec, 155679605 t fired, . Pages in use: 359 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 367/2000 Raft-PT-06-CTLFireability-2024-03 86922267 m, 370677 m/sec, 159088326 t fired, . Pages in use: 367 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 374/2000 Raft-PT-06-CTLFireability-2024-03 88562870 m, 328120 m/sec, 162137406 t fired, . Pages in use: 374 Visible: 16 CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 375/2000 Raft-PT-06-CTLFireability-2024-03 88828199 m, 53065 m/sec, 162632946 t fired, . Pages in use: 375 Visible: 16 EXCL) for Raft-PT-06-CTLFireability-2024-03 (local timeout) CATEGORY VALUE PRODUCED BY[0m INITIAL true preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFAG 0 1 0 0 3 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 7 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 375 Visible: 16 for 53 Raft-PT-06-CTLFireability-2023-15 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Raft-PT-06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Raft-PT-06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662340500434"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Raft-PT-06.tgz
mv Raft-PT-06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;