fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r313-tall-171662339800148
Last Updated
July 7, 2024

About the Execution of LoLA for RERS17pb113-PT-5

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16205.296 1150444.00 2869284.00 2619.30 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r313-tall-171662339800148.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RERS17pb113-PT-5, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662339800148
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 8.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K May 19 07:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 19 16:14 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K May 19 07:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.0K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 93K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 2 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 15M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-00
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-01
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-02
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-03
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-04
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-05
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-06
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-07
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-08
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-09
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-10
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-11
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-12
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-13
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-14
FORMULA_NAME RERS17pb113-PT-5-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717254079568


BK_STOP 1717255230012

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 21 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 26 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 31 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 36 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 41 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 46 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 51 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 56 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 61 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 66 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 71 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 76 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 81 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 86 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 91 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 96 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 101 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 106 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 111 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 116 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 121 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 126 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 131 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 136 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 141 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 146 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 151 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 156 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 161 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 166 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 171 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 176 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 181 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 186 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 191 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 196 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 201 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 206 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 211 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 216 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 221 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 226 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 231 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 236 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 241 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 246 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 251 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 256 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 261 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 266 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 271 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 276 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 281 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 286 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 291 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 296 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 301 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 35 (type EXCL) for 34 RERS17pb113-PT-5-LTLFireability-10
[lola][I] time limit : 194 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 4/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 228 m, 45 m/sec, 227 t fired, .
[lola][.]
[lola][.] Time elapsed: 306 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 9/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 485 m, 51 m/sec, 484 t fired, .
[lola][.]
[lola][.] Time elapsed: 311 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 14/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 710 m, 45 m/sec, 709 t fired, .
[lola][.]
[lola][.] Time elapsed: 316 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 56 (type EQUN) for 10 RERS17pb113-PT-5-LTLFireability-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 19/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 895 m, 37 m/sec, 894 t fired, .
[lola][.] 56 EF STEQ 2/3281 0/5 RERS17pb113-PT-5-LTLFireability-02 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 321 secs. Pages in use: 1
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 24/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 1153 m, 51 m/sec, 1152 t fired, .
[lola][.] 56 EF STEQ 7/3281 0/5 RERS17pb113-PT-5-LTLFireability-02 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 326 secs. Pages in use: 1
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 29/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 1405 m, 50 m/sec, 1404 t fired, .
[lola][.] 56 EF STEQ 12/3281 0/5 RERS17pb113-PT-5-LTLFireability-02 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 331 secs. Pages in use: 1
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 34/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 1600 m, 39 m/sec, 1599 t fired, .
[lola][.] 56 EF STEQ 17/3281 0/5 RERS17pb113-PT-5-LTLFireability-02 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 336 secs. Pages in use: 1
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 39/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 1841 m, 48 m/sec, 1840 t fired, .
[lola][.] 56 EF STEQ 22/3281 0/5 RERS17pb113-PT-5-LTLFireability-02 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 341 secs. Pages in use: 1
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 44/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 2131 m, 58 m/sec, 2130 t fired, .
[lola][.] 56 EF STEQ 27/3281 0/5 RERS17pb113-PT-5-LTLFireability-02 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 346 secs. Pages in use: 1
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I] FINISHED task # 56 (type EQUN) for RERS17pb113-PT-5-LTLFireability-02
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 49/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 2305 m, 34 m/sec, 2304 t fired, .
[lola][.]
[lola][.] Time elapsed: 351 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 54/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 2603 m, 59 m/sec, 2602 t fired, .
[lola][.]
[lola][.] Time elapsed: 356 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 59/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 2948 m, 69 m/sec, 2947 t fired, .
[lola][.]
[lola][.] Time elapsed: 361 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 64/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 3323 m, 75 m/sec, 3322 t fired, .
[lola][.]
[lola][.] Time elapsed: 366 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 69/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 3620 m, 59 m/sec, 3619 t fired, .
[lola][.]
[lola][.] Time elapsed: 371 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 74/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 3836 m, 43 m/sec, 3835 t fired, .
[lola][.]
[lola][.] Time elapsed: 376 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 79/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 4076 m, 48 m/sec, 4075 t fired, .
[lola][.]
[lola][.] Time elapsed: 381 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 84/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 4399 m, 64 m/sec, 4398 t fired, .
[lola][.]
[lola][.] Time elapsed: 386 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 89/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 4738 m, 67 m/sec, 4737 t fired, .
[lola][.]
[lola][.] Time elapsed: 391 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 94/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 5118 m, 76 m/sec, 5117 t fired, .
[lola][.]
[lola][.] Time elapsed: 396 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 99/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 5316 m, 39 m/sec, 5315 t fired, .
[lola][.]
[lola][.] Time elapsed: 401 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 104/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 5539 m, 44 m/sec, 5538 t fired, .
[lola][.]
[lola][.] Time elapsed: 406 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 109/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 5823 m, 56 m/sec, 5822 t fired, .
[lola][.]
[lola][.] Time elapsed: 411 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 114/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 6046 m, 44 m/sec, 6045 t fired, .
[lola][.]
[lola][.] Time elapsed: 416 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 119/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 6344 m, 59 m/sec, 6343 t fired, .
[lola][.]
[lola][.] Time elapsed: 421 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 124/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 6609 m, 53 m/sec, 6608 t fired, .
[lola][.]
[lola][.] Time elapsed: 426 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 129/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 6919 m, 62 m/sec, 6918 t fired, .
[lola][.]
[lola][.] Time elapsed: 431 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 134/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 7219 m, 60 m/sec, 7218 t fired, .
[lola][.]
[lola][.] Time elapsed: 436 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 139/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 7620 m, 80 m/sec, 7619 t fired, .
[lola][.]
[lola][.] Time elapsed: 441 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 144/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 8021 m, 80 m/sec, 8020 t fired, .
[lola][.]
[lola][.] Time elapsed: 446 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 149/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 8418 m, 79 m/sec, 8417 t fired, .
[lola][.]
[lola][.] Time elapsed: 451 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 154/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 8806 m, 77 m/sec, 8805 t fired, .
[lola][.]
[lola][.] Time elapsed: 456 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 159/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 9193 m, 77 m/sec, 9192 t fired, .
[lola][.]
[lola][.] Time elapsed: 461 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 164/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 9587 m, 78 m/sec, 9586 t fired, .
[lola][.]
[lola][.] Time elapsed: 466 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 169/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 10005 m, 83 m/sec, 10004 t fired, .
[lola][.]
[lola][.] Time elapsed: 471 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 174/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 10400 m, 79 m/sec, 10399 t fired, .
[lola][.]
[lola][.] Time elapsed: 476 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 179/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 10794 m, 78 m/sec, 10793 t fired, .
[lola][.]
[lola][.] Time elapsed: 481 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 184/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 11203 m, 81 m/sec, 11202 t fired, .
[lola][.]
[lola][.] Time elapsed: 486 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 189/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 11600 m, 79 m/sec, 11599 t fired, .
[lola][.]
[lola][.] Time elapsed: 491 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 194/194 1/2000 RERS17pb113-PT-5-LTLFireability-10 11973 m, 74 m/sec, 11972 t fired, .
[lola][.]
[lola][.] Time elapsed: 496 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][W] CANCELED task # 35 (type EXCL) for RERS17pb113-PT-5-LTLFireability-10 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 1 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 501 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 50 (type EXCL) for 49 RERS17pb113-PT-5-LTLFireability-15
[lola][I] time limit : 193 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 35 (type EXCL) for 34 RERS17pb113-PT-5-LTLFireability-10
[lola][I] time limit : 3099 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 5/3099 1/5 RERS17pb113-PT-5-LTLFireability-10 269 m, -2340 m/sec, 268 t fired, .
[lola][.] 50 LTL EXCL 5/193 4/2000 RERS17pb113-PT-5-LTLFireability-15 193854 m, 38770 m/sec, 193886 t fired, .
[lola][.]
[lola][.] Time elapsed: 506 secs. Pages in use: 7
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 10/3099 1/5 RERS17pb113-PT-5-LTLFireability-10 584 m, 63 m/sec, 583 t fired, .
[lola][.] 50 LTL EXCL 10/182 7/2000 RERS17pb113-PT-5-LTLFireability-15 388682 m, 38965 m/sec, 388713 t fired, .
[lola][.]
[lola][.] Time elapsed: 511 secs. Pages in use: 10
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I] FINISHED task # 50 (type EXCL) for RERS17pb113-PT-5-LTLFireability-15
[lola][I] result : false
[lola][I] markings : 428215
[lola][I] fired transitions : 428247
[lola][I] time used : 11
[lola][I] memory pages used : 7
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 15/193 1/5 RERS17pb113-PT-5-LTLFireability-10 865 m, 56 m/sec, 864 t fired, .
[lola][.]
[lola][.] Time elapsed: 516 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 20/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1113 m, 49 m/sec, 1112 t fired, .
[lola][.]
[lola][.] Time elapsed: 521 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 25/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1393 m, 56 m/sec, 1392 t fired, .
[lola][.]
[lola][.] Time elapsed: 526 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 30/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1591 m, 39 m/sec, 1590 t fired, .
[lola][.]
[lola][.] Time elapsed: 531 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 35/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1824 m, 46 m/sec, 1823 t fired, .
[lola][.]
[lola][.] Time elapsed: 536 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 40/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2096 m, 54 m/sec, 2095 t fired, .
[lola][.]
[lola][.] Time elapsed: 541 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 45/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2271 m, 35 m/sec, 2270 t fired, .
[lola][.]
[lola][.] Time elapsed: 546 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 50/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2521 m, 50 m/sec, 2520 t fired, .
[lola][.]
[lola][.] Time elapsed: 551 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 55/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2840 m, 63 m/sec, 2839 t fired, .
[lola][.]
[lola][.] Time elapsed: 556 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 60/193 1/5 RERS17pb113-PT-5-LTLFireability-10 3174 m, 66 m/sec, 3173 t fired, .
[lola][.]
[lola][.] Time elapsed: 561 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 65/193 1/5 RERS17pb113-PT-5-LTLFireability-10 3519 m, 69 m/sec, 3518 t fired, .
[lola][.]
[lola][.] Time elapsed: 566 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 70/193 1/5 RERS17pb113-PT-5-LTLFireability-10 3765 m, 49 m/sec, 3764 t fired, .
[lola][.]
[lola][.] Time elapsed: 571 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 75/193 1/5 RERS17pb113-PT-5-LTLFireability-10 4029 m, 52 m/sec, 4028 t fired, .
[lola][.]
[lola][.] Time elapsed: 576 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 80/193 1/5 RERS17pb113-PT-5-LTLFireability-10 4284 m, 51 m/sec, 4283 t fired, .
[lola][.]
[lola][.] Time elapsed: 581 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 85/193 1/5 RERS17pb113-PT-5-LTLFireability-10 4586 m, 60 m/sec, 4585 t fired, .
[lola][.]
[lola][.] Time elapsed: 586 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 90/193 1/5 RERS17pb113-PT-5-LTLFireability-10 4907 m, 64 m/sec, 4906 t fired, .
[lola][.]
[lola][.] Time elapsed: 591 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 95/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5201 m, 58 m/sec, 5200 t fired, .
[lola][.]
[lola][.] Time elapsed: 596 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 100/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5423 m, 44 m/sec, 5422 t fired, .
[lola][.]
[lola][.] Time elapsed: 601 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 105/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5700 m, 55 m/sec, 5699 t fired, .
[lola][.]
[lola][.] Time elapsed: 606 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 110/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5920 m, 44 m/sec, 5919 t fired, .
[lola][.]
[lola][.] Time elapsed: 611 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 115/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6190 m, 54 m/sec, 6189 t fired, .
[lola][.]
[lola][.] Time elapsed: 616 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 120/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6507 m, 63 m/sec, 6506 t fired, .
[lola][.]
[lola][.] Time elapsed: 621 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 125/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6754 m, 49 m/sec, 6753 t fired, .
[lola][.]
[lola][.] Time elapsed: 626 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 130/193 1/5 RERS17pb113-PT-5-LTLFireability-10 7055 m, 60 m/sec, 7054 t fired, .
[lola][.]
[lola][.] Time elapsed: 631 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 135/193 1/5 RERS17pb113-PT-5-LTLFireability-10 7343 m, 57 m/sec, 7342 t fired, .
[lola][.]
[lola][.] Time elapsed: 636 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 140/193 1/5 RERS17pb113-PT-5-LTLFireability-10 7706 m, 72 m/sec, 7705 t fired, .
[lola][.]
[lola][.] Time elapsed: 641 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 145/193 1/5 RERS17pb113-PT-5-LTLFireability-10 8096 m, 78 m/sec, 8095 t fired, .
[lola][.]
[lola][.] Time elapsed: 646 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 150/193 1/5 RERS17pb113-PT-5-LTLFireability-10 8483 m, 77 m/sec, 8482 t fired, .
[lola][.]
[lola][.] Time elapsed: 651 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 155/193 1/5 RERS17pb113-PT-5-LTLFireability-10 8866 m, 76 m/sec, 8865 t fired, .
[lola][.]
[lola][.] Time elapsed: 656 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 160/193 1/5 RERS17pb113-PT-5-LTLFireability-10 9253 m, 77 m/sec, 9252 t fired, .
[lola][.]
[lola][.] Time elapsed: 661 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 165/193 1/5 RERS17pb113-PT-5-LTLFireability-10 9646 m, 78 m/sec, 9645 t fired, .
[lola][.]
[lola][.] Time elapsed: 666 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 170/193 1/5 RERS17pb113-PT-5-LTLFireability-10 10041 m, 79 m/sec, 10040 t fired, .
[lola][.]
[lola][.] Time elapsed: 671 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 175/193 1/5 RERS17pb113-PT-5-LTLFireability-10 10426 m, 77 m/sec, 10425 t fired, .
[lola][.]
[lola][.] Time elapsed: 676 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 180/193 1/5 RERS17pb113-PT-5-LTLFireability-10 10827 m, 80 m/sec, 10826 t fired, .
[lola][.]
[lola][.] Time elapsed: 681 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 185/193 1/5 RERS17pb113-PT-5-LTLFireability-10 11216 m, 77 m/sec, 11215 t fired, .
[lola][.]
[lola][.] Time elapsed: 686 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 190/193 1/5 RERS17pb113-PT-5-LTLFireability-10 11604 m, 77 m/sec, 11603 t fired, .
[lola][.]
[lola][.] Time elapsed: 691 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][W] CANCELED task # 35 (type EXCL) for RERS17pb113-PT-5-LTLFireability-10 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 1 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 696 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 47 (type EXCL) for 46 RERS17pb113-PT-5-LTLFireability-14
[lola][I] time limit : 193 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 35 (type EXCL) for 34 RERS17pb113-PT-5-LTLFireability-10
[lola][I] time limit : 2904 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 5/2904 1/5 RERS17pb113-PT-5-LTLFireability-10 289 m, -2263 m/sec, 288 t fired, .
[lola][.] 47 LTL EXCL 5/193 4/2000 RERS17pb113-PT-5-LTLFireability-14 198218 m, 39643 m/sec, 198217 t fired, .
[lola][.]
[lola][.] Time elapsed: 701 secs. Pages in use: 10
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I] FINISHED task # 47 (type EXCL) for RERS17pb113-PT-5-LTLFireability-14
[lola][I] result : false
[lola][I] markings : 228245
[lola][I] fired transitions : 228245
[lola][I] time used : 6
[lola][I] memory pages used : 4
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 10/193 1/5 RERS17pb113-PT-5-LTLFireability-10 641 m, 70 m/sec, 640 t fired, .
[lola][.]
[lola][.] Time elapsed: 706 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 15/193 1/5 RERS17pb113-PT-5-LTLFireability-10 900 m, 51 m/sec, 899 t fired, .
[lola][.]
[lola][.] Time elapsed: 711 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 20/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1183 m, 56 m/sec, 1182 t fired, .
[lola][.]
[lola][.] Time elapsed: 716 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 25/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1428 m, 49 m/sec, 1427 t fired, .
[lola][.]
[lola][.] Time elapsed: 721 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 30/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1649 m, 44 m/sec, 1648 t fired, .
[lola][.]
[lola][.] Time elapsed: 726 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 35/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1894 m, 49 m/sec, 1893 t fired, .
[lola][.]
[lola][.] Time elapsed: 731 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 40/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2169 m, 55 m/sec, 2168 t fired, .
[lola][.]
[lola][.] Time elapsed: 736 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 45/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2364 m, 39 m/sec, 2363 t fired, .
[lola][.]
[lola][.] Time elapsed: 741 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 50/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2675 m, 62 m/sec, 2674 t fired, .
[lola][.]
[lola][.] Time elapsed: 746 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 55/193 1/5 RERS17pb113-PT-5-LTLFireability-10 3062 m, 77 m/sec, 3061 t fired, .
[lola][.]
[lola][.] Time elapsed: 751 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 60/193 1/5 RERS17pb113-PT-5-LTLFireability-10 3457 m, 79 m/sec, 3456 t fired, .
[lola][.]
[lola][.] Time elapsed: 756 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 65/193 1/5 RERS17pb113-PT-5-LTLFireability-10 3748 m, 58 m/sec, 3747 t fired, .
[lola][.]
[lola][.] Time elapsed: 761 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 70/193 1/5 RERS17pb113-PT-5-LTLFireability-10 4034 m, 57 m/sec, 4033 t fired, .
[lola][.]
[lola][.] Time elapsed: 766 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 75/193 1/5 RERS17pb113-PT-5-LTLFireability-10 4328 m, 58 m/sec, 4327 t fired, .
[lola][.]
[lola][.] Time elapsed: 771 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 80/193 1/5 RERS17pb113-PT-5-LTLFireability-10 4627 m, 59 m/sec, 4626 t fired, .
[lola][.]
[lola][.] Time elapsed: 776 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 85/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5003 m, 75 m/sec, 5002 t fired, .
[lola][.]
[lola][.] Time elapsed: 781 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 90/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5258 m, 51 m/sec, 5257 t fired, .
[lola][.]
[lola][.] Time elapsed: 786 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 95/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5472 m, 42 m/sec, 5471 t fired, .
[lola][.]
[lola][.] Time elapsed: 791 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 100/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5772 m, 60 m/sec, 5771 t fired, .
[lola][.]
[lola][.] Time elapsed: 796 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 105/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6006 m, 46 m/sec, 6005 t fired, .
[lola][.]
[lola][.] Time elapsed: 801 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 110/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6294 m, 57 m/sec, 6293 t fired, .
[lola][.]
[lola][.] Time elapsed: 806 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 115/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6566 m, 54 m/sec, 6565 t fired, .
[lola][.]
[lola][.] Time elapsed: 811 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 120/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6864 m, 59 m/sec, 6863 t fired, .
[lola][.]
[lola][.] Time elapsed: 816 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 125/193 1/5 RERS17pb113-PT-5-LTLFireability-10 7137 m, 54 m/sec, 7136 t fired, .
[lola][.]
[lola][.] Time elapsed: 821 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 130/193 1/5 RERS17pb113-PT-5-LTLFireability-10 7492 m, 71 m/sec, 7491 t fired, .
[lola][.]
[lola][.] Time elapsed: 826 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 135/193 1/5 RERS17pb113-PT-5-LTLFireability-10 7880 m, 77 m/sec, 7879 t fired, .
[lola][.]
[lola][.] Time elapsed: 831 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 140/193 1/5 RERS17pb113-PT-5-LTLFireability-10 8289 m, 81 m/sec, 8288 t fired, .
[lola][.]
[lola][.] Time elapsed: 836 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 145/193 1/5 RERS17pb113-PT-5-LTLFireability-10 8689 m, 80 m/sec, 8688 t fired, .
[lola][.]
[lola][.] Time elapsed: 841 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 150/193 1/5 RERS17pb113-PT-5-LTLFireability-10 9094 m, 81 m/sec, 9093 t fired, .
[lola][.]
[lola][.] Time elapsed: 846 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 155/193 1/5 RERS17pb113-PT-5-LTLFireability-10 9491 m, 79 m/sec, 9490 t fired, .
[lola][.]
[lola][.] Time elapsed: 851 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 160/193 1/5 RERS17pb113-PT-5-LTLFireability-10 9884 m, 78 m/sec, 9883 t fired, .
[lola][.]
[lola][.] Time elapsed: 856 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 165/193 1/5 RERS17pb113-PT-5-LTLFireability-10 10292 m, 81 m/sec, 10291 t fired, .
[lola][.]
[lola][.] Time elapsed: 861 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 170/193 1/5 RERS17pb113-PT-5-LTLFireability-10 10698 m, 81 m/sec, 10697 t fired, .
[lola][.]
[lola][.] Time elapsed: 866 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 175/193 1/5 RERS17pb113-PT-5-LTLFireability-10 11119 m, 84 m/sec, 11118 t fired, .
[lola][.]
[lola][.] Time elapsed: 871 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 180/193 1/5 RERS17pb113-PT-5-LTLFireability-10 11524 m, 81 m/sec, 11523 t fired, .
[lola][.]
[lola][.] Time elapsed: 876 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 185/193 1/5 RERS17pb113-PT-5-LTLFireability-10 11934 m, 82 m/sec, 11933 t fired, .
[lola][.]
[lola][.] Time elapsed: 881 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 190/193 1/5 RERS17pb113-PT-5-LTLFireability-10 12380 m, 89 m/sec, 12379 t fired, .
[lola][.]
[lola][.] Time elapsed: 886 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][W] CANCELED task # 35 (type EXCL) for RERS17pb113-PT-5-LTLFireability-10 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 1 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 891 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 44 (type EXCL) for 43 RERS17pb113-PT-5-LTLFireability-13
[lola][I] time limit : 193 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 35 (type EXCL) for 34 RERS17pb113-PT-5-LTLFireability-10
[lola][I] time limit : 2709 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 44 (type EXCL) for RERS17pb113-PT-5-LTLFireability-13
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 5/193 1/5 RERS17pb113-PT-5-LTLFireability-10 238 m, -2428 m/sec, 237 t fired, .
[lola][.]
[lola][.] Time elapsed: 896 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 10/193 1/5 RERS17pb113-PT-5-LTLFireability-10 506 m, 53 m/sec, 505 t fired, .
[lola][.]
[lola][.] Time elapsed: 901 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 15/193 1/5 RERS17pb113-PT-5-LTLFireability-10 760 m, 50 m/sec, 759 t fired, .
[lola][.]
[lola][.] Time elapsed: 906 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 20/193 1/5 RERS17pb113-PT-5-LTLFireability-10 961 m, 40 m/sec, 960 t fired, .
[lola][.]
[lola][.] Time elapsed: 911 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 25/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1208 m, 49 m/sec, 1207 t fired, .
[lola][.]
[lola][.] Time elapsed: 916 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 30/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1425 m, 43 m/sec, 1424 t fired, .
[lola][.]
[lola][.] Time elapsed: 921 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 35/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1616 m, 38 m/sec, 1615 t fired, .
[lola][.]
[lola][.] Time elapsed: 926 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 40/193 1/5 RERS17pb113-PT-5-LTLFireability-10 1821 m, 41 m/sec, 1820 t fired, .
[lola][.]
[lola][.] Time elapsed: 931 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 45/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2073 m, 50 m/sec, 2072 t fired, .
[lola][.]
[lola][.] Time elapsed: 936 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 50/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2270 m, 39 m/sec, 2269 t fired, .
[lola][.]
[lola][.] Time elapsed: 941 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 55/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2556 m, 57 m/sec, 2555 t fired, .
[lola][.]
[lola][.] Time elapsed: 946 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 60/193 1/5 RERS17pb113-PT-5-LTLFireability-10 2909 m, 70 m/sec, 2908 t fired, .
[lola][.]
[lola][.] Time elapsed: 951 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 65/193 1/5 RERS17pb113-PT-5-LTLFireability-10 3280 m, 74 m/sec, 3279 t fired, .
[lola][.]
[lola][.] Time elapsed: 956 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 70/193 1/5 RERS17pb113-PT-5-LTLFireability-10 3618 m, 67 m/sec, 3617 t fired, .
[lola][.]
[lola][.] Time elapsed: 961 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 75/193 1/5 RERS17pb113-PT-5-LTLFireability-10 3859 m, 48 m/sec, 3858 t fired, .
[lola][.]
[lola][.] Time elapsed: 966 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 80/193 1/5 RERS17pb113-PT-5-LTLFireability-10 4144 m, 57 m/sec, 4143 t fired, .
[lola][.]
[lola][.] Time elapsed: 971 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 85/193 1/5 RERS17pb113-PT-5-LTLFireability-10 4433 m, 57 m/sec, 4432 t fired, .
[lola][.]
[lola][.] Time elapsed: 976 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 90/193 1/5 RERS17pb113-PT-5-LTLFireability-10 4752 m, 63 m/sec, 4751 t fired, .
[lola][.]
[lola][.] Time elapsed: 981 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 95/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5110 m, 71 m/sec, 5109 t fired, .
[lola][.]
[lola][.] Time elapsed: 986 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 100/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5285 m, 35 m/sec, 5284 t fired, .
[lola][.]
[lola][.] Time elapsed: 991 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 105/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5523 m, 47 m/sec, 5522 t fired, .
[lola][.]
[lola][.] Time elapsed: 996 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 110/193 1/5 RERS17pb113-PT-5-LTLFireability-10 5790 m, 53 m/sec, 5789 t fired, .
[lola][.]
[lola][.] Time elapsed: 1001 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 115/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6021 m, 46 m/sec, 6020 t fired, .
[lola][.]
[lola][.] Time elapsed: 1006 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 120/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6321 m, 60 m/sec, 6320 t fired, .
[lola][.]
[lola][.] Time elapsed: 1011 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 125/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6610 m, 57 m/sec, 6609 t fired, .
[lola][.]
[lola][.] Time elapsed: 1016 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 130/193 1/5 RERS17pb113-PT-5-LTLFireability-10 6927 m, 63 m/sec, 6926 t fired, .
[lola][.]
[lola][.] Time elapsed: 1021 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 135/193 1/5 RERS17pb113-PT-5-LTLFireability-10 7239 m, 62 m/sec, 7238 t fired, .
[lola][.]
[lola][.] Time elapsed: 1026 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 140/193 1/5 RERS17pb113-PT-5-LTLFireability-10 7637 m, 79 m/sec, 7636 t fired, .
[lola][.]
[lola][.] Time elapsed: 1031 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 145/193 1/5 RERS17pb113-PT-5-LTLFireability-10 8054 m, 83 m/sec, 8053 t fired, .
[lola][.]
[lola][.] Time elapsed: 1036 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 150/193 1/5 RERS17pb113-PT-5-LTLFireability-10 8481 m, 85 m/sec, 8480 t fired, .
[lola][.]
[lola][.] Time elapsed: 1041 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 155/193 1/5 RERS17pb113-PT-5-LTLFireability-10 8889 m, 81 m/sec, 8888 t fired, .
[lola][.]
[lola][.] Time elapsed: 1046 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 160/193 1/5 RERS17pb113-PT-5-LTLFireability-10 9288 m, 79 m/sec, 9287 t fired, .
[lola][.]
[lola][.] Time elapsed: 1051 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 165/193 1/5 RERS17pb113-PT-5-LTLFireability-10 9706 m, 83 m/sec, 9705 t fired, .
[lola][.]
[lola][.] Time elapsed: 1056 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 170/193 1/5 RERS17pb113-PT-5-LTLFireability-10 10122 m, 83 m/sec, 10121 t fired, .
[lola][.]
[lola][.] Time elapsed: 1061 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 175/193 1/5 RERS17pb113-PT-5-LTLFireability-10 10545 m, 84 m/sec, 10544 t fired, .
[lola][.]
[lola][.] Time elapsed: 1066 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 180/193 1/5 RERS17pb113-PT-5-LTLFireability-10 10965 m, 84 m/sec, 10964 t fired, .
[lola][.]
[lola][.] Time elapsed: 1071 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 185/193 1/5 RERS17pb113-PT-5-LTLFireability-10 11373 m, 81 m/sec, 11372 t fired, .
[lola][.]
[lola][.] Time elapsed: 1076 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 190/193 1/5 RERS17pb113-PT-5-LTLFireability-10 11759 m, 77 m/sec, 11758 t fired, .
[lola][.]
[lola][.] Time elapsed: 1081 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][W] CANCELED task # 35 (type EXCL) for RERS17pb113-PT-5-LTLFireability-10 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 0 0 1 1 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 1086 secs. Pages in use: 10
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 38 (type EXCL) for 37 RERS17pb113-PT-5-LTLFireability-11
[lola][I] time limit : 193 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 35 (type EXCL) for 34 RERS17pb113-PT-5-LTLFireability-10
[lola][I] time limit : 2514 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 5/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 227 m, -2306 m/sec, 226 t fired, .
[lola][.] 38 LTL EXCL 5/193 2/2000 RERS17pb113-PT-5-LTLFireability-11 121995 m, 24399 m/sec, 121995 t fired, .
[lola][.]
[lola][.] Time elapsed: 1091 secs. Pages in use: 11
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 10/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 401 m, 34 m/sec, 400 t fired, .
[lola][.] 38 LTL EXCL 10/179 3/2000 RERS17pb113-PT-5-LTLFireability-11 248102 m, 25221 m/sec, 248102 t fired, .
[lola][.]
[lola][.] Time elapsed: 1096 secs. Pages in use: 12
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 15/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 623 m, 44 m/sec, 622 t fired, .
[lola][.] 38 LTL EXCL 15/179 5/2000 RERS17pb113-PT-5-LTLFireability-11 379597 m, 26299 m/sec, 379596 t fired, .
[lola][.]
[lola][.] Time elapsed: 1101 secs. Pages in use: 14
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 20/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 797 m, 34 m/sec, 796 t fired, .
[lola][.] 38 LTL EXCL 20/179 6/2000 RERS17pb113-PT-5-LTLFireability-11 509991 m, 26078 m/sec, 510005 t fired, .
[lola][.]
[lola][.] Time elapsed: 1106 secs. Pages in use: 15
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 25/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 940 m, 28 m/sec, 939 t fired, .
[lola][.] 38 LTL EXCL 25/179 8/2000 RERS17pb113-PT-5-LTLFireability-11 638176 m, 25637 m/sec, 638189 t fired, .
[lola][.]
[lola][.] Time elapsed: 1111 secs. Pages in use: 17
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 30/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 1132 m, 38 m/sec, 1131 t fired, .
[lola][.] 38 LTL EXCL 30/179 9/2000 RERS17pb113-PT-5-LTLFireability-11 767812 m, 25927 m/sec, 767827 t fired, .
[lola][.]
[lola][.] Time elapsed: 1116 secs. Pages in use: 18
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 35/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 1321 m, 37 m/sec, 1320 t fired, .
[lola][.] 38 LTL EXCL 35/179 10/2000 RERS17pb113-PT-5-LTLFireability-11 893607 m, 25159 m/sec, 893622 t fired, .
[lola][.]
[lola][.] Time elapsed: 1121 secs. Pages in use: 19
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 40/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 1459 m, 27 m/sec, 1458 t fired, .
[lola][.] 38 LTL EXCL 40/179 12/2000 RERS17pb113-PT-5-LTLFireability-11 1026465 m, 26571 m/sec, 1026480 t fired, .
[lola][.]
[lola][.] Time elapsed: 1126 secs. Pages in use: 21
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 45/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 1618 m, 31 m/sec, 1617 t fired, .
[lola][.] 38 LTL EXCL 45/179 13/2000 RERS17pb113-PT-5-LTLFireability-11 1164430 m, 27593 m/sec, 1164445 t fired, .
[lola][.]
[lola][.] Time elapsed: 1131 secs. Pages in use: 22
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 50/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 1806 m, 37 m/sec, 1805 t fired, .
[lola][.] 38 LTL EXCL 50/179 15/2000 RERS17pb113-PT-5-LTLFireability-11 1294784 m, 26070 m/sec, 1294799 t fired, .
[lola][.]
[lola][.] Time elapsed: 1136 secs. Pages in use: 24
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 55/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 1997 m, 38 m/sec, 1996 t fired, .
[lola][.] 38 LTL EXCL 55/179 16/2000 RERS17pb113-PT-5-LTLFireability-11 1427214 m, 26486 m/sec, 1427229 t fired, .
[lola][.]
[lola][.] Time elapsed: 1141 secs. Pages in use: 25
[lola][.] # running tasks: 2 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] RERS17pb113-PT-5-LTLFireability-13: LTL true LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-5-LTLFireability-15: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-02: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 35 LTL EXCL 60/2514 1/5 RERS17pb113-PT-5-LTLFireability-10 2146 m, 29 m/sec, 2145 t fired, .
[lola][.] 38 LTL EXCL 60/179 17/2000 RERS17pb113-PT-5-LTLFireability-11 1548096 m, 24176 m/sec, 1548113 t fired, .
[lola][.]
[lola][.] Time elapsed: 1146 secs. Pages in use: 26
[lola][.] # running tasks: 2 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-5"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-5, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662339800148"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-5.tgz
mv RERS17pb113-PT-5 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;