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Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r313-tall-171662339800145
Last Updated
July 7, 2024

About the Execution of LoLA for RERS17pb113-PT-5

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16072.888 887751.00 1203657.00 1822.50 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r313-tall-171662339800145.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RERS17pb113-PT-5, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662339800145
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 8.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K May 19 07:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 19 16:14 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K May 19 07:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.0K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 93K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 2 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 15M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-00
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-01
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-02
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-03
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-04
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-05
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-06
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-07
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-08
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-09
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-10
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2024-11
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2023-12
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2023-13
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2023-14
FORMULA_NAME RERS17pb113-PT-5-CTLCardinality-2023-15

=== Now, execution of the tool begins

BK_START 1717253514277


BK_STOP 1717254402028

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLCardinality.xml
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-00: DISJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-01: DISJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-02: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-04: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-05: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-07: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-09: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-15: DISJ 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
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[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-00: DISJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-01: DISJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-02: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-04: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-05: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-07: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-09: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-15: DISJ 0 0 0 0 0 0 0 0
[lola][.]
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[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-00: DISJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-01: DISJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-02: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-04: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-05: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-07: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-15: DISJ 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-00: DISJ 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-01: DISJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-02: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-03: CTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-15: DISJ 0 0 0 0 0 0 0 0
[lola][.]
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[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-02: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-04: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-05: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-07: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-09: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-14: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-15: DISJ 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-01: DISJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-02: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-03: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-04: CTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-09: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-11: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-12: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-13: CTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2023-14: CTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-02: CONJ 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-03: CTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-5-CTLCardinality-2024-03: CTL 0 0 0 0 0 0 0 0
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-5"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-5, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662339800145"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-5.tgz
mv RERS17pb113-PT-5 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;