fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r313-tall-171662339800140
Last Updated
July 7, 2024

About the Execution of LoLA for RERS17pb113-PT-4

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16207.344 1019870.00 796109.00 7702.30 ???????????????T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r313-tall-171662339800140.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RERS17pb113-PT-4, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662339800140
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 16M
-rw-r--r-- 1 mcc users 6.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.8K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K May 19 16:14 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 19 07:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 19 18:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 147K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 90K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 2 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 15M May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-00
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-01
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-02
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-03
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-04
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-05
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-06
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-07
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-08
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-09
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-10
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-11
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-12
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-13
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-14
FORMULA_NAME RERS17pb113-PT-4-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717253127357

FORMULA RERS17pb113-PT-4-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717254147227

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-4-LTLFireability-00: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F 0 0 0 0 0 0 0 0
[lola][.]
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[lola][.]
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] RERS17pb113-PT-4-LTLFireability-00: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F 0 0 0 0 0 0 0 0
[lola][.]
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[lola][.] RERS17pb113-PT-4-LTLFireability-00: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F 0 0 0 0 0 0 0 0
[lola][.]
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[lola][.] RERS17pb113-PT-4-LTLFireability-00: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-00: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-00: F 0 0 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 0 0 0 0 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-00: F 0 0 0 0 1 0 0 0
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[lola][.] 49 EG EXCL 3/206 0/2000 RERS17pb113-PT-4-LTLFireability-15 --
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[lola][.] RERS17pb113-PT-4-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 49 EG EXCL 8/206 0/2000 RERS17pb113-PT-4-LTLFireability-15 --
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[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 LTL EXCL 1/219 1/2000 RERS17pb113-PT-4-LTLFireability-10 17904 m, 3580 m/sec, 17903 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 31 LTL EXCL 6/219 3/2000 RERS17pb113-PT-4-LTLFireability-10 157101 m, 27839 m/sec, 157100 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.] RERS17pb113-PT-4-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 43 LTL EXCL 1/234 1/2000 RERS17pb113-PT-4-LTLFireability-14 47289 m, 9457 m/sec, 47288 t fired, .
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[lola][I] LAUNCH task # 40 (type EXCL) for 39 RERS17pb113-PT-4-LTLFireability-13
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 40 LTL EXCL 3/252 2/2000 RERS17pb113-PT-4-LTLFireability-13 122792 m, 24558 m/sec, 122792 t fired, .
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[lola][I] LAUNCH task # 37 (type EXCL) for 36 RERS17pb113-PT-4-LTLFireability-12
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.] RERS17pb113-PT-4-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 37 LTL EXCL 0/273 1/2000 RERS17pb113-PT-4-LTLFireability-12 18707 m, 3741 m/sec, 18706 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
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[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 37 LTL EXCL 5/273 4/2000 RERS17pb113-PT-4-LTLFireability-12 224457 m, 41150 m/sec, 224456 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 1 0 0 2 0 0 0
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[lola][.] RERS17pb113-PT-4-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 37 LTL EXCL 10/273 6/2000 RERS17pb113-PT-4-LTLFireability-12 416925 m, 38493 m/sec, 496034 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 1 0 0 2 0 0 0
[lola][.] RERS17pb113-PT-4-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
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[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 37 LTL EXCL 15/273 9/2000 RERS17pb113-PT-4-LTLFireability-12 610854 m, 38785 m/sec, 745691 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.] 37 LTL EXCL 20/273 11/2000 RERS17pb113-PT-4-LTLFireability-12 798430 m, 37515 m/sec, 1010006 t fired, .
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[lola][.] 37 LTL EXCL 25/273 13/2000 RERS17pb113-PT-4-LTLFireability-12 989684 m, 38250 m/sec, 1248656 t fired, .
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[lola][.] 37 LTL EXCL 30/273 16/2000 RERS17pb113-PT-4-LTLFireability-12 1177584 m, 37580 m/sec, 1470505 t fired, .
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[lola][.] 37 LTL EXCL 35/273 18/2000 RERS17pb113-PT-4-LTLFireability-12 1363915 m, 37266 m/sec, 1705548 t fired, .
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[lola][.] 37 LTL EXCL 40/273 20/2000 RERS17pb113-PT-4-LTLFireability-12 1547842 m, 36785 m/sec, 1964597 t fired, .
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[lola][.] 37 LTL EXCL 45/273 23/2000 RERS17pb113-PT-4-LTLFireability-12 1741048 m, 38641 m/sec, 2157956 t fired, .
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[lola][.] 37 LTL EXCL 50/273 26/2000 RERS17pb113-PT-4-LTLFireability-12 1932936 m, 38377 m/sec, 2349865 t fired, .
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[lola][.] 37 LTL EXCL 55/273 28/2000 RERS17pb113-PT-4-LTLFireability-12 2107075 m, 34827 m/sec, 2652163 t fired, .
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[lola][.] 37 LTL EXCL 75/273 35/2000 RERS17pb113-PT-4-LTLFireability-12 2817850 m, 37090 m/sec, 3782846 t fired, .
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[lola][.] 37 LTL EXCL 130/273 56/2000 RERS17pb113-PT-4-LTLFireability-12 4812121 m, 36633 m/sec, 6712094 t fired, .
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[lola][.] 37 LTL EXCL 135/273 58/2000 RERS17pb113-PT-4-LTLFireability-12 4991936 m, 35963 m/sec, 6995692 t fired, .
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[lola][I] LAUNCH task # 13 (type EXCL) for 12 RERS17pb113-PT-4-LTLFireability-04
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
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[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.]
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[lola][.] 13 LTL EXCL 32/267 1/2000 RERS17pb113-PT-4-LTLFireability-04 132 m, 26 m/sec, 131 t fired, .
[lola][.] 37 LTL EXCL 19/2943 0/5 RERS17pb113-PT-4-LTLFireability-12 --
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[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.]
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[lola][.] 13 LTL EXCL 80/267 1/2000 RERS17pb113-PT-4-LTLFireability-04 728 m, 119 m/sec, 727 t fired, .
[lola][.] 37 LTL EXCL 68/244 1/5 RERS17pb113-PT-4-LTLFireability-12 555 m, -1147406 m/sec, 554 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
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[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
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[lola][.] 13 LTL EXCL 126/267 1/2000 RERS17pb113-PT-4-LTLFireability-04 1621 m, 178 m/sec, 1621 t fired, .
[lola][.] 37 LTL EXCL 114/244 1/5 RERS17pb113-PT-4-LTLFireability-12 1586 m, 206 m/sec, 1585 t fired, .
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[lola][.] 13 LTL EXCL 165/267 1/2000 RERS17pb113-PT-4-LTLFireability-04 3497 m, 375 m/sec, 3496 t fired, .
[lola][.] 37 LTL EXCL 153/244 1/5 RERS17pb113-PT-4-LTLFireability-12 3125 m, 307 m/sec, 3124 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-15: F true state space / EG
[lola][.]
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[lola][.] 13 LTL EXCL 198/267 1/2000 RERS17pb113-PT-4-LTLFireability-04 3996 m, 99 m/sec, 3996 t fired, .
[lola][.] 37 LTL EXCL 186/244 1/5 RERS17pb113-PT-4-LTLFireability-12 3608 m, 96 m/sec, 3607 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
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[lola][.] RERS17pb113-PT-4-LTLFireability-06: F 0 1 0 0 2 0 0 0
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[lola][.] 13 LTL EXCL 232/267 1/2000 RERS17pb113-PT-4-LTLFireability-04 4512 m, 103 m/sec, 4512 t fired, .
[lola][.] 37 LTL EXCL 220/244 1/5 RERS17pb113-PT-4-LTLFireability-12 4084 m, 95 m/sec, 4084 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
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[lola][.] 13 LTL EXCL 263/267 1/2000 RERS17pb113-PT-4-LTLFireability-04 5030 m, 103 m/sec, 5029 t fired, .
[lola][.] 37 LTL EXCL 251/244 1/5 RERS17pb113-PT-4-LTLFireability-12 4569 m, 97 m/sec, 4568 t fired, .
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
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[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
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[lola][.] RERS17pb113-PT-4-LTLFireability-10: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-13: LTL false LTL model checker
[lola][.] RERS17pb113-PT-4-LTLFireability-14: LTL false LTL model checker
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[lola][.] 4 LTL EXCL 49/264 1/2000 RERS17pb113-PT-4-LTLFireability-01 579 m, 115 m/sec, 578 t fired, .
[lola][.] 13 LTL EXCL 26/2629 0/5 RERS17pb113-PT-4-LTLFireability-04 --
[lola][.] 37 LTL EXCL 36/2645 0/5 RERS17pb113-PT-4-LTLFireability-12 --
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-4"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-4, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662339800140"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-4.tgz
mv RERS17pb113-PT-4 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;