About the Execution of LoLA for RERS17pb113-PT-4
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.695 | 379336.00 | 784862.00 | 1050.50 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662339800138.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is RERS17pb113-PT-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662339800138
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 16M
-rw-r--r-- 1 mcc users 6.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.8K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K May 19 16:14 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 19 07:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 19 18:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 147K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 90K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 2 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 15M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-00
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-01
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-02
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-03
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-04
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-05
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-06
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-07
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-08
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-09
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-10
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2024-11
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2023-12
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2023-13
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2023-14
FORMULA_NAME RERS17pb113-PT-4-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717252685276
BK_STOP 1717253064612
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-02: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-07: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2024-11: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] RERS17pb113-PT-4-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 416 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662339800138"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-4.tgz
mv RERS17pb113-PT-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;