About the Execution of LoLA for QuasiCertifProtocol-PT-22
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
0.000 | 2945040.00 | 0.00 | 0.00 | ????T?F???????T? | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662339700090.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is QuasiCertifProtocol-PT-22, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662339700090
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.9M
-rw-r--r-- 1 mcc users 74K Apr 13 04:15 CTLCardinality.txt
-rw-r--r-- 1 mcc users 496K Apr 13 04:15 CTLCardinality.xml
-rw-r--r-- 1 mcc users 17K Apr 13 04:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 109K Apr 13 04:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 81K Apr 23 07:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 339K Apr 23 07:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Apr 23 07:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 38K Apr 23 07:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 141K Apr 13 04:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 906K Apr 13 04:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 20K Apr 13 04:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 123K Apr 13 04:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 7.6K Apr 23 07:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 22K Apr 23 07:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 503K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-00
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-01
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-02
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-03
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-04
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-05
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-06
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-07
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-08
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-09
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-10
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-11
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-12
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-13
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-14
FORMULA_NAME QuasiCertifProtocol-PT-22-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717241840289
FORMULA QuasiCertifProtocol-PT-22-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-PT-22-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-PT-22-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717244785329
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 13 (type CNST) for 12 QuasiCertifProtocol-PT-22-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 66 (type SKEL/FNDP) for 22 QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type SKEL/EQUN) for 22 QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/SRCH) for 22 QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 66 (type SKEL/FNDP) for QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 67 (type EQUN) for QuasiCertifProtocol-PT-22-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][W] CANCELED task # 68 (type SRCH) for QuasiCertifProtocol-PT-22-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][I] FINISHED task # 13 (type CNST) for QuasiCertifProtocol-PT-22-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 67 (type SKEL/EQUN) for QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 72 (type EXCL) for 22 QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 149 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 70 (type FNDP) for 22 QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 22 QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 72 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 70 (type FNDP) for QuasiCertifProtocol-PT-22-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][W] CANCELED task # 71 (type EQUN) for QuasiCertifProtocol-PT-22-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][I] FINISHED task # 70 (type FNDP) for QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 71 (type EQUN) for QuasiCertifProtocol-PT-22-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 QuasiCertifProtocol-PT-22-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 74 (type FNDP) for 46 QuasiCertifProtocol-PT-22-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 75 (type EQUN) for 46 QuasiCertifProtocol-PT-22-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 80 (type EQUN) for 15 QuasiCertifProtocol-PT-22-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type FNDP) for QuasiCertifProtocol-PT-22-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 75 (type EQUN) for QuasiCertifProtocol-PT-22-CTLFireability-2024-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 85 (type EQUN) for 15 QuasiCertifProtocol-PT-22-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 80 (type EQUN) for QuasiCertifProtocol-PT-22-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 85 (type EQUN) for QuasiCertifProtocol-PT-22-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 75 (type EQUN) for QuasiCertifProtocol-PT-22-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 4/239 2/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 265768 m, 53153 m/sec, 1652078 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 9/239 5/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 647203 m, 76287 m/sec, 3712230 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 14/239 5/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 647203 m, 0 m/sec, 5810900 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 19/239 5/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 647203 m, 0 m/sec, 7908913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 24/239 7/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 1069663 m, 84492 m/sec, 9935144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 29/239 9/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 1245286 m, 35124 m/sec, 11949145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 34/239 9/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 1245286 m, 0 m/sec, 13997510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 39/239 10/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 1403640 m, 31670 m/sec, 16020536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 44/239 12/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 1796254 m, 78522 m/sec, 18026664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 49/239 12/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 1796254 m, 0 m/sec, 20059216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 54/239 12/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 1796254 m, 0 m/sec, 22116792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 59/239 15/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 2251221 m, 90993 m/sec, 24034765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 64/239 18/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 2723702 m, 94496 m/sec, 26002418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 69/239 21/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 3162938 m, 87847 m/sec, 27955547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 74/239 23/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 3620108 m, 91434 m/sec, 29887579 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 79/239 26/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 4024040 m, 80786 m/sec, 31838099 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 84/239 28/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 4418874 m, 78966 m/sec, 33778477 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 89/239 31/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 4856057 m, 87436 m/sec, 35707260 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 94/239 34/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 5258803 m, 80549 m/sec, 37656808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 99/239 36/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 5647650 m, 77769 m/sec, 39599219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 104/239 39/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6011229 m, 72715 m/sec, 41551490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 109/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 36427 m/sec, 43506562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 114/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 45408302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 119/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 47398844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 124/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 49366292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 129/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 51257737 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 134/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 53294485 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 139/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 55253154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 144/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 57165027 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 149/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 59184136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 154/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 61129361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 159/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 63129897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 164/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 65092844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 169/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 67031762 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 174/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 69007645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 179/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 70967480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 184/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 72944909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 189/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 74955998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 194/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 76900532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 199/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 78901922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 204/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 80843302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 209/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 82852324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 214/239 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6193365 m, 0 m/sec, 84813943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 219/239 42/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6477051 m, 56737 m/sec, 86754262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 224/239 44/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6791569 m, 62903 m/sec, 88702903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 229/239 44/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6791569 m, 0 m/sec, 90634611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 234/239 44/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 6791569 m, 0 m/sec, 92643830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 239/239 46/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 7233102 m, 88306 m/sec, 94567359 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 4 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-01 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 57 QuasiCertifProtocol-PT-22-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 QuasiCertifProtocol-PT-22-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 3355 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 25
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/239 3/5 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 383216 m, -1369977 m/sec, 2117867 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/239 5/5 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 647203 m, 52797 m/sec, 4192427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/239 5/5 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 647203 m, 0 m/sec, 6292881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 20/239 5/5 QuasiCertifProtocol-PT-22-CTLFireability-2024-01 694364 m, 9432 m/sec, 8373053 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 4 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-01 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 QuasiCertifProtocol-PT-22-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 76
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 QuasiCertifProtocol-PT-22-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 277 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 5/277 3/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 325060 m, 65012 m/sec, 2142167 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 10/277 5/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 590677 m, 53123 m/sec, 4242127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 15/277 6/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 875634 m, 56991 m/sec, 6295876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 20/277 8/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 1141698 m, 53212 m/sec, 8352191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 25/277 10/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 1416875 m, 55035 m/sec, 10396277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 30/277 11/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 1681315 m, 52888 m/sec, 12438790 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 35/277 13/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 1953415 m, 54420 m/sec, 14460716 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 40/277 15/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 2245021 m, 58321 m/sec, 16403699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 45/277 17/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 2521531 m, 55302 m/sec, 18459421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 50/277 18/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 2761921 m, 48078 m/sec, 20421971 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 55/277 19/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 3013714 m, 50358 m/sec, 22436496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 60/277 21/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 3231087 m, 43474 m/sec, 24430852 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 65/277 22/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 3478804 m, 49543 m/sec, 26370729 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 70/277 24/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 3720938 m, 48426 m/sec, 28366750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 75/277 25/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 3925135 m, 40839 m/sec, 30325502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 80/277 27/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 4150197 m, 45012 m/sec, 32358004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 85/277 28/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 4356073 m, 41175 m/sec, 34323087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 90/277 29/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 4601340 m, 49053 m/sec, 36253936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 95/277 31/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 4831468 m, 46025 m/sec, 38220246 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 100/277 32/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 5038208 m, 41348 m/sec, 40174309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 105/277 34/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 5256781 m, 43714 m/sec, 42173096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 110/277 35/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 5450190 m, 38681 m/sec, 44119089 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 115/277 36/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 5672788 m, 44519 m/sec, 46123717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 120/277 38/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 5854522 m, 36346 m/sec, 48068800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 125/277 39/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 6055690 m, 40233 m/sec, 50081967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 130/277 41/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 6239272 m, 36716 m/sec, 52061033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 135/277 42/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 6522432 m, 56632 m/sec, 54012081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 140/277 44/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 6770852 m, 49684 m/sec, 56015403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 145/277 45/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 7051287 m, 56087 m/sec, 57989719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 150/277 47/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 7300418 m, 49826 m/sec, 59986994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 155/277 48/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 7577173 m, 55351 m/sec, 61906028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 160/277 50/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 7848730 m, 54311 m/sec, 63779150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 165/277 51/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 8094479 m, 49149 m/sec, 65706917 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 170/277 52/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 8336482 m, 48400 m/sec, 67600205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 175/277 54/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 8577279 m, 48159 m/sec, 69537465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 180/277 55/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 8781761 m, 40896 m/sec, 71434243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 185/277 56/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 9023203 m, 48288 m/sec, 73322899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 190/277 57/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 9260828 m, 47525 m/sec, 75280579 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 195/277 58/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 9456053 m, 39045 m/sec, 77184441 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 200/277 59/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 9679955 m, 44780 m/sec, 79166207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 205/277 60/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 9873124 m, 38633 m/sec, 81087070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 210/277 62/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 10117402 m, 48855 m/sec, 83011677 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 215/277 63/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 10357063 m, 47932 m/sec, 84987212 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 220/277 65/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 10557225 m, 40032 m/sec, 86912922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 225/277 66/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 10779864 m, 44527 m/sec, 88911708 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 230/277 67/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 10970308 m, 38088 m/sec, 90853776 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 235/277 69/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 11192203 m, 44379 m/sec, 92843464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 240/277 70/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 11373332 m, 36225 m/sec, 94772032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 245/277 72/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 11575760 m, 40485 m/sec, 96780096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 250/277 73/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 11738673 m, 32582 m/sec, 98724643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 255/277 74/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 12022362 m, 56737 m/sec, 100683284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 260/277 76/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 12268725 m, 49272 m/sec, 102666369 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 265/277 77/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 12553405 m, 56936 m/sec, 104576650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 270/277 79/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 12823474 m, 54013 m/sec, 106439153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 275/277 80/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 13051992 m, 45703 m/sec, 108309101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 38 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 QuasiCertifProtocol-PT-22-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 277 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 QuasiCertifProtocol-PT-22-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 3050 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 5/277 3/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 319347 m, 63869 m/sec, 2104353 t fired, .
[[35mlola[0m][.] 38 CTL EXCL 5/3050 3/5 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 322551 m, -2545888 m/sec, 2123550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 10/277 5/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 586444 m, 53419 m/sec, 4209993 t fired, .
[[35mlola[0m][.] 38 CTL EXCL 10/254 5/5 QuasiCertifProtocol-PT-22-CTLFireability-2024-11 588711 m, 53232 m/sec, 4225108 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 38 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 15/277 6/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 872336 m, 57178 m/sec, 6270054 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 20/277 8/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 1139406 m, 53414 m/sec, 8332803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 25/277 10/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 1415062 m, 55131 m/sec, 10385537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 30/277 11/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 1681369 m, 53261 m/sec, 12439623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 35/277 13/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 1954625 m, 54651 m/sec, 14473729 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 40/277 15/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 2248307 m, 58736 m/sec, 16431840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 45/277 17/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 2524386 m, 55215 m/sec, 18495423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 50/277 18/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 2767820 m, 48686 m/sec, 20463978 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 55/277 20/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 3020193 m, 50474 m/sec, 22482887 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 60/277 21/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 3238492 m, 43659 m/sec, 24480774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 65/277 22/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 3487972 m, 49896 m/sec, 26440239 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 70/277 24/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 3731326 m, 48670 m/sec, 28464131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 75/277 25/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 3941704 m, 42075 m/sec, 30457472 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 80/277 27/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 4166057 m, 44870 m/sec, 32508618 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 85/277 28/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 4377722 m, 42333 m/sec, 34486117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 90/277 29/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 4627298 m, 49915 m/sec, 36458939 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 95/277 31/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 4849826 m, 44505 m/sec, 38441202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 100/277 32/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 5070009 m, 44036 m/sec, 40440305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 105/277 34/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 5284306 m, 42859 m/sec, 42456095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 110/277 35/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 5481296 m, 39398 m/sec, 44433763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 115/277 37/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 5709089 m, 45558 m/sec, 46469691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 120/277 38/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 5894369 m, 37056 m/sec, 48456956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 125/277 39/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 6093744 m, 39875 m/sec, 50494808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 130/277 41/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 6311158 m, 43482 m/sec, 52485521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 135/277 42/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 6577328 m, 53234 m/sec, 54441363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 140/277 44/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 6827652 m, 50064 m/sec, 56450745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 145/277 46/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 7099915 m, 54452 m/sec, 58415861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 150/277 47/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 7343615 m, 48740 m/sec, 60424830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 155/277 49/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 7633576 m, 57992 m/sec, 62317797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 160/277 50/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 7914830 m, 56250 m/sec, 64232365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 165/277 51/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 8141890 m, 45412 m/sec, 66144977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 170/277 53/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 8386951 m, 49012 m/sec, 68032333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 175/277 54/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 8628881 m, 48386 m/sec, 69996814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 180/277 55/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 8843773 m, 42978 m/sec, 71897269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 185/277 56/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 9087873 m, 48820 m/sec, 73814612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 190/277 57/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 9305645 m, 43554 m/sec, 75745157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 195/277 58/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 9516530 m, 42177 m/sec, 77684575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 200/277 60/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 9728682 m, 42430 m/sec, 79647146 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 205/277 61/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 9935027 m, 41269 m/sec, 81565751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 210/277 62/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 10184775 m, 49949 m/sec, 83514278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 215/277 64/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 10401339 m, 43312 m/sec, 85463214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 220/277 65/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 10618661 m, 43464 m/sec, 87431161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 225/277 66/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 10828684 m, 42004 m/sec, 89406446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 230/277 68/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 11019331 m, 38129 m/sec, 91343125 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 235/277 69/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 11245485 m, 45230 m/sec, 93345167 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 240/277 70/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 11424042 m, 35711 m/sec, 95279432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 245/277 72/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 11622674 m, 39726 m/sec, 97277494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 250/277 73/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 11822178 m, 39900 m/sec, 99220123 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 255/277 75/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 12086896 m, 52943 m/sec, 101177792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 260/277 76/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 12333054 m, 49231 m/sec, 103157576 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 265/277 78/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 12615926 m, 56574 m/sec, 105032213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 270/277 79/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 12894843 m, 55783 m/sec, 106956111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 275/277 80/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 13122462 m, 45523 m/sec, 108854460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 29 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-08 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 QuasiCertifProtocol-PT-22-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 277 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 QuasiCertifProtocol-PT-22-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 2770 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 78
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 5/277 3/5 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 330456 m, -2558401 m/sec, 2178914 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 10/277 5/5 QuasiCertifProtocol-PT-22-CTLFireability-2024-08 600030 m, 53914 m/sec, 4321705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 29 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-08 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 QuasiCertifProtocol-PT-22-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 306 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 367
[[35mlola[0m][I] fired transitions : 380
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 QuasiCertifProtocol-PT-22-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 344 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 62
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 82 (type EXCL) for 15 QuasiCertifProtocol-PT-22-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 393 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 82 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 29
[[35mlola[0m][I] fired transitions : 28
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 77 (type EXCL) for 15 QuasiCertifProtocol-PT-22-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 459 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 77 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 29
[[35mlola[0m][I] fired transitions : 28
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 57 QuasiCertifProtocol-PT-22-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 551 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 5/551 3/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 333011 m, 66602 m/sec, 2198648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 10/551 5/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 600920 m, 53581 m/sec, 4327593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 15/551 6/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 889740 m, 57764 m/sec, 6396094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 20/551 8/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 1158217 m, 53695 m/sec, 8478095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 25/551 10/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 1433559 m, 55068 m/sec, 10518157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 30/551 11/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 1699566 m, 53201 m/sec, 12576119 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 35/551 13/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 1974464 m, 54979 m/sec, 14601527 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 40/551 14/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 2267249 m, 58557 m/sec, 16564108 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 45/551 16/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 2536523 m, 53854 m/sec, 18627133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 50/551 18/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 2785864 m, 49868 m/sec, 20597078 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 55/551 19/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 3037460 m, 50319 m/sec, 22628531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 60/551 21/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 3259332 m, 44374 m/sec, 24630289 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 65/551 22/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 3511543 m, 50442 m/sec, 26602921 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 70/551 24/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 3747299 m, 47151 m/sec, 28630681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 75/551 25/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 3961684 m, 42877 m/sec, 30650494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 80/551 26/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 4185573 m, 44777 m/sec, 32708154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 85/551 28/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 4399370 m, 42759 m/sec, 34694985 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 90/551 29/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 4655224 m, 51170 m/sec, 36688934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 95/551 31/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 4871426 m, 43240 m/sec, 38684913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 100/551 32/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 5100639 m, 45842 m/sec, 40715855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 105/551 34/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 5309679 m, 41808 m/sec, 42733793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 110/551 35/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 5516529 m, 41370 m/sec, 44735074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 115/551 36/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 5740569 m, 44808 m/sec, 46782683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 120/551 38/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 5929409 m, 37768 m/sec, 48804721 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 125/551 39/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 6124793 m, 39076 m/sec, 50843240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 130/551 41/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 6369130 m, 48867 m/sec, 52843630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 135/551 42/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 6633744 m, 52922 m/sec, 54839427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 140/551 44/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 6893886 m, 52028 m/sec, 56848559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 145/551 45/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 7156721 m, 52567 m/sec, 58810722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 150/551 47/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 7407510 m, 50157 m/sec, 60800962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 155/551 48/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 7690971 m, 56692 m/sec, 62678181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 160/551 50/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 7968218 m, 55449 m/sec, 64615159 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 165/551 51/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 8198827 m, 46121 m/sec, 66537160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 276
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 170/551 52/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 8442115 m, 48657 m/sec, 68447175 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 279
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 175/551 53/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 8673237 m, 46224 m/sec, 70408892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 282
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 180/551 54/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 8894376 m, 44227 m/sec, 72313299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 185/551 56/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 9142148 m, 49554 m/sec, 74265010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 289
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 190/551 57/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 9344489 m, 40468 m/sec, 76197348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 195/551 58/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 9574598 m, 46021 m/sec, 78190755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 200/551 59/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 9775319 m, 40144 m/sec, 80160350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 298
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 205/551 60/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 10005857 m, 46107 m/sec, 82107667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 301
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 210/551 62/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 10255403 m, 49909 m/sec, 84092148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 215/551 63/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 10461427 m, 41204 m/sec, 86052733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 308
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 220/551 65/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 10689460 m, 45606 m/sec, 88062065 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 225/551 66/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 10882680 m, 38644 m/sec, 90033292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 230/551 67/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 11100540 m, 43572 m/sec, 92026337 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 318
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 235/551 69/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 11312787 m, 42449 m/sec, 94031912 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 240/551 70/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 11501593 m, 37761 m/sec, 96026670 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 324
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 245/551 72/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 11687762 m, 37233 m/sec, 98012055 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 328
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 250/551 73/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 11922573 m, 46962 m/sec, 99945249 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 255/551 74/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 12176029 m, 50691 m/sec, 101903390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 260/551 76/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 12442203 m, 53234 m/sec, 103870685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 338
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 265/551 77/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 12720428 m, 55645 m/sec, 105750623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 341
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 270/551 79/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 12992731 m, 54460 m/sec, 107713790 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 345
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 275/551 80/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 13220801 m, 45614 m/sec, 109638387 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 280/551 81/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 13472220 m, 50283 m/sec, 111593719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 285/551 82/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 13673076 m, 40171 m/sec, 113508555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 354
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 290/551 83/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 13923831 m, 50151 m/sec, 115450418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 357
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 295/551 85/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 14176740 m, 50581 m/sec, 117472072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 362
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 300/551 86/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 14383045 m, 41261 m/sec, 119440826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 364
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 305/551 87/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 14610613 m, 45513 m/sec, 121483444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 368
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 310/551 88/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 14804009 m, 38679 m/sec, 123461277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 315/551 89/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 15055526 m, 50303 m/sec, 125414107 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 373
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 320/551 91/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 15299798 m, 48854 m/sec, 127429600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 375
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 325/551 92/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 15504935 m, 41027 m/sec, 129401228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 376
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 330/551 93/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 15727668 m, 44546 m/sec, 131400111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 377
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 335/551 94/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 15917264 m, 37919 m/sec, 133334471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 340/551 96/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 16142253 m, 44997 m/sec, 135350566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 345/551 97/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 16324483 m, 36446 m/sec, 137308150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 381
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 350/551 98/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 16532457 m, 41594 m/sec, 139350062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 355/551 100/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 16704630 m, 34434 m/sec, 141318007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 384
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 360/551 101/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 16986608 m, 56395 m/sec, 143202376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 385
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 365/551 102/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 17268240 m, 56326 m/sec, 145098272 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 386
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 370/551 103/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 17488439 m, 44039 m/sec, 146960311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 375/551 105/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 17736005 m, 49513 m/sec, 148866817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 389
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 380/551 106/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 17973292 m, 47457 m/sec, 150796480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 390
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 385/551 107/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 18186560 m, 42653 m/sec, 152683922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 391
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 390/551 108/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 18428563 m, 48400 m/sec, 154590617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 392
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 395/551 110/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 18645269 m, 43341 m/sec, 156482728 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 394
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 400/551 111/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 18857035 m, 42353 m/sec, 158458191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 395
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 405/551 112/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 19076492 m, 43891 m/sec, 160482691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 396
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 410/551 113/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 19287636 m, 42228 m/sec, 162441553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 397
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 415/551 114/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 19536732 m, 49819 m/sec, 164386139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 398
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 420/551 115/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 19749856 m, 42624 m/sec, 166306562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 399
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 425/551 116/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 19968863 m, 43801 m/sec, 168288694 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 400
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 430/551 118/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 20179730 m, 42173 m/sec, 170277549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 402
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 435/551 119/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 20374849 m, 39023 m/sec, 172226341 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 403
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 440/551 120/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 20599572 m, 44944 m/sec, 174240731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 404
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 445/551 121/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 20782298 m, 36545 m/sec, 176206187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 405
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 450/551 122/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 20983345 m, 40209 m/sec, 178252638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 406
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 455/551 124/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 21199235 m, 43178 m/sec, 180224532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 408
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 460/551 125/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 21476020 m, 55357 m/sec, 182093026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 409
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 465/551 126/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 21741893 m, 53174 m/sec, 183986327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 410
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 470/551 128/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 21976338 m, 46889 m/sec, 185829752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 412
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 475/551 129/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 22248664 m, 54465 m/sec, 187697115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 480/551 130/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 22465463 m, 43359 m/sec, 189513268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 414
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 485/551 131/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 22737525 m, 54412 m/sec, 191362307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 415
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 490/551 132/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 22945070 m, 41509 m/sec, 193147265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 416
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 495/551 133/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 23205492 m, 52084 m/sec, 194971375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 417
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 500/551 135/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 23427912 m, 44484 m/sec, 196849728 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 419
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 505/551 136/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 23681774 m, 50772 m/sec, 198893280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 420
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 510/551 138/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 23904901 m, 44625 m/sec, 200909958 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 422
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 515/551 139/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 24082283 m, 35476 m/sec, 202863392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 423
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 520/551 140/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 24321498 m, 47843 m/sec, 204746882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 424
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 525/551 142/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 24554411 m, 46582 m/sec, 206615217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 426
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 530/551 143/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 24750480 m, 39213 m/sec, 208454878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 427
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 535/551 144/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 24985865 m, 47077 m/sec, 210325247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 428
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 540/551 145/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 25178865 m, 38600 m/sec, 212152904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 429
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 545/551 146/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 25410352 m, 46297 m/sec, 214003314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 430
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 CTL EXCL 550/551 147/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 25606020 m, 39133 m/sec, 215846666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 431
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 60 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 QuasiCertifProtocol-PT-22-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 550 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 57 QuasiCertifProtocol-PT-22-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 2200 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 5/550 2/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 256729 m, 51345 m/sec, 2182490 t fired, .
[[35mlola[0m][.] 60 CTL EXCL 5/2200 3/5 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 327397 m, -5055724 m/sec, 2160400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 10/550 4/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 485978 m, 45849 m/sec, 4336641 t fired, .
[[35mlola[0m][.] 60 CTL EXCL 10/440 5/5 QuasiCertifProtocol-PT-22-CTLFireability-2024-15 597157 m, 53952 m/sec, 4295536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 60 (type EXCL) for QuasiCertifProtocol-PT-22-CTLFireability-2024-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 15/550 5/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 694258 m, 41656 m/sec, 6490462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 20/550 7/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 939764 m, 49101 m/sec, 8620889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 25/550 8/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 1155211 m, 43089 m/sec, 10762258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 30/550 9/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 1383729 m, 45703 m/sec, 12889152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 35/550 11/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 1605578 m, 44369 m/sec, 15018746 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 40/550 12/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 1811691 m, 41222 m/sec, 17152380 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 45/550 13/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 2057689 m, 49199 m/sec, 19219300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 50/550 14/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 2288967 m, 46255 m/sec, 21276503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 55/550 16/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 2514899 m, 45186 m/sec, 23420368 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 60/550 17/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 2708926 m, 38805 m/sec, 25475439 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 65/550 18/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 2924612 m, 43137 m/sec, 27554862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 70/550 20/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 3124669 m, 40011 m/sec, 29662909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 75/550 21/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 3313575 m, 37781 m/sec, 31708114 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 80/550 22/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 3523957 m, 42076 m/sec, 33771486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 85/550 24/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 3726613 m, 40531 m/sec, 35871407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 90/550 25/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 3902724 m, 35222 m/sec, 37931726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 95/550 26/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 4098853 m, 39225 m/sec, 40063943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 100/550 27/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 4262840 m, 32797 m/sec, 42143214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 105/550 28/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 4474537 m, 42339 m/sec, 44192251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 110/550 29/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 4682171 m, 41526 m/sec, 46269285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 115/550 31/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 4864678 m, 36501 m/sec, 48327844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 120/550 32/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 5051499 m, 37364 m/sec, 50396230 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 125/550 33/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 5240555 m, 37811 m/sec, 52494704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 130/550 34/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 5406090 m, 33107 m/sec, 54544124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 135/550 35/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 5597520 m, 38286 m/sec, 56636288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 140/550 37/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 5777628 m, 36021 m/sec, 58723255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 145/550 38/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 5943956 m, 33265 m/sec, 60819732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 150/550 39/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 6112033 m, 33615 m/sec, 62922741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 155/550 40/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 6297302 m, 37053 m/sec, 65002201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 160/550 41/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 6523580 m, 45255 m/sec, 67066120 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 165/550 43/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 6736343 m, 42552 m/sec, 69174207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 170/550 44/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 6954059 m, 43543 m/sec, 71217873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 175/550 45/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 7174413 m, 44070 m/sec, 73284207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 180/550 47/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 7375910 m, 40299 m/sec, 75359671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 185/550 48/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 7612987 m, 47415 m/sec, 77361898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 190/550 49/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 7835342 m, 44471 m/sec, 79338517 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 195/550 50/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 8050789 m, 43089 m/sec, 81377491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1595 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 200/550 51/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 8241515 m, 38145 m/sec, 83368475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1600 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 205/550 52/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 8446480 m, 40993 m/sec, 85369996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1605 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 210/550 53/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 8643342 m, 39372 m/sec, 87407875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1610 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 215/550 54/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 8826011 m, 36533 m/sec, 89396579 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1615 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 220/550 55/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 9023635 m, 39524 m/sec, 91369870 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1620 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 225/550 56/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 9227705 m, 40814 m/sec, 93426201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1625 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 230/550 57/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 9399807 m, 34420 m/sec, 95428033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1630 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 235/550 58/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 9586513 m, 37341 m/sec, 97479520 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1635 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 240/550 59/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 9761947 m, 35086 m/sec, 99514176 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1640 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 245/550 60/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 9942843 m, 36179 m/sec, 101518798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 250/550 61/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 10148683 m, 41168 m/sec, 103528188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1650 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 255/550 63/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 10345843 m, 39432 m/sec, 105571350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1655 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 260/550 64/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 10519748 m, 34781 m/sec, 107583354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1660 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 265/550 65/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 10707065 m, 37463 m/sec, 109647678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1665 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 270/550 66/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 10873142 m, 33215 m/sec, 111666278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1670 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 275/550 67/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 11051733 m, 35718 m/sec, 113691750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1675 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 280/550 68/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 11237813 m, 37216 m/sec, 115753005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1680 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 285/550 69/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 11392139 m, 30865 m/sec, 117746824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1685 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 290/550 71/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 11566597 m, 34891 m/sec, 119811992 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1690 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 295/550 72/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 11716542 m, 29989 m/sec, 121825412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1695 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 300/550 73/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 11929188 m, 42529 m/sec, 123840348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1700 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 305/550 74/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 12145803 m, 43323 m/sec, 125889362 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1705 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 310/550 75/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 12347288 m, 40297 m/sec, 127937144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1710 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 315/550 77/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 12576552 m, 45852 m/sec, 129906496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1715 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 320/550 78/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 12797502 m, 44190 m/sec, 131864553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1720 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 325/550 79/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 13007268 m, 41953 m/sec, 133846263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1725 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 330/550 80/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 13193391 m, 37224 m/sec, 135801751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1730 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 335/550 81/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 13396362 m, 40594 m/sec, 137775669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1735 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 340/550 82/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 13587446 m, 38216 m/sec, 139748110 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1740 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 345/550 83/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 13765634 m, 35637 m/sec, 141701714 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1745 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 350/550 84/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 13964498 m, 39772 m/sec, 143672956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1750 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 355/550 85/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 14167678 m, 40636 m/sec, 145725819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1755 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 360/550 86/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 14338968 m, 34258 m/sec, 147722111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1760 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 365/550 87/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 14526091 m, 37424 m/sec, 149762023 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1765 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 370/550 88/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 14700846 m, 34951 m/sec, 151785400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1770 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 375/550 89/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 14880399 m, 35910 m/sec, 153783049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1775 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 380/550 90/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 15083289 m, 40578 m/sec, 155781047 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1780 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 385/550 91/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 15281343 m, 39610 m/sec, 157814596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1785 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 390/550 92/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 15453424 m, 34416 m/sec, 159804889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1790 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 395/550 93/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 15639321 m, 37179 m/sec, 161840348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1795 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 400/550 93/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 15806451 m, 33426 m/sec, 163836291 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1800 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 405/550 94/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 15976803 m, 34070 m/sec, 165849301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1805 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 410/550 96/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 16169614 m, 38562 m/sec, 167939571 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1810 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 415/550 97/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 16324311 m, 30939 m/sec, 169947976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1815 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 420/550 98/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 16501574 m, 35452 m/sec, 172031775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1820 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 425/550 99/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 16654206 m, 30526 m/sec, 174065566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1825 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 430/550 100/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 16862159 m, 41590 m/sec, 176071759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1830 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 435/550 101/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 17088683 m, 45304 m/sec, 178028079 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1835 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 440/550 103/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 17311299 m, 44523 m/sec, 180021071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1840 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 445/550 104/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 17490880 m, 35916 m/sec, 181951029 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1845 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 450/550 105/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 17696184 m, 41060 m/sec, 183931431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1850 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 455/550 106/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 17898252 m, 40413 m/sec, 185936424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1855 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 460/550 106/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 18065052 m, 33360 m/sec, 187879914 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1860 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 465/550 108/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 18271910 m, 41371 m/sec, 189884717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1865 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 470/550 109/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 18474244 m, 40466 m/sec, 191886171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1870 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 475/550 110/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 18650825 m, 35316 m/sec, 193848385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1875 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-06: AG false state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-PT-22-CTLFireability-2024-15: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 480/550 110/2000 QuasiCertifProtocol-PT-22-CTLFireability-2024-09 18830524 m, 35939 m/sec, 195868522 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1880 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-PT-22-CTLFireability-2024-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-PT-22-CTLFireability-2024-05: DISJ false DISJ[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-PT-22"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is QuasiCertifProtocol-PT-22, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662339700090"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-PT-22.tgz
mv QuasiCertifProtocol-PT-22 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;