About the Execution of LoLA for QuasiCertifProtocol-COL-18
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
11734.191 | 3600000.00 | 3729450.00 | 10583.70 | ??????????T??T?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r313-tall-171662339600026.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is QuasiCertifProtocol-COL-18, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r313-tall-171662339600026
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 7.9K Apr 13 04:07 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Apr 13 04:07 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Apr 13 04:00 CTLFireability.txt
-rw-r--r-- 1 mcc users 85K Apr 13 04:00 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 23 07:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 23 07:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 23 07:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Apr 23 07:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.9K Apr 13 04:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 62K Apr 13 04:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Apr 13 04:10 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 55K Apr 13 04:10 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 07:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 93K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-00
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-01
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-02
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-03
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-04
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-05
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-06
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-07
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-08
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-09
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-10
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-11
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-12
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-13
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-14
FORMULA_NAME QuasiCertifProtocol-COL-18-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717231872188
FORMULA QuasiCertifProtocol-COL-18-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA QuasiCertifProtocol-COL-18-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 61 (type SKEL/FNDP) for 38 QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type SKEL/EQUN) for 38 QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type SKEL/SRCH) for 38 QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type SKEL/FNDP) for 51 QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type SKEL/SRCH) for QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 43
[[35mlola[0m][I] fired transitions : 42
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 61 (type SKEL/FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 62 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][I] LAUNCH task # 66 (type SKEL/EQUN) for 51 QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type SKEL/SRCH) for 51 QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type SKEL/FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 66 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][W] CANCELED task # 67 (type SRCH) for QuasiCertifProtocol-COL-18-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][I] Places: 1398, Transitions: 296
[[35mlola[0m][W] findlow criterion violated for transition 22
[[35mlola[0m][I] FINISHED task # 62 (type SKEL/EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 66 (type SKEL/EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][W] findlow criterion violated for transition 21
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 70 (type EXCL) for 38 QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 68 (type FNDP) for 38 QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 69 (type EQUN) for 38 QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 43
[[35mlola[0m][I] fired transitions : 42
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 68 (type FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][W] CANCELED task # 69 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][W] findlow criterion violated for transition 16
[[35mlola[0m][I] LAUNCH task # 73 (type EXCL) for 51 QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 180 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 71 (type FNDP) for 51 QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 51 QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 41
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 71 (type FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][W] CANCELED task # 72 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][I] FINISHED task # 71 (type FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[*** LOG ERROR #0001 ***] [2024-06-01 08:51:13] [status_logger] string pointer is null
[[35mlola[0m][I] FINISHED task # 68 (type FNDP) for QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] findlow criterion violated for 9 clusters
[[35mlola[0m][I] Time for checking findlow: 1
[[35mlola[0m][I] FINISHED task # 69 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for QuasiCertifProtocol-COL-18-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 QuasiCertifProtocol-COL-18-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 74 (type SKEL/SRCH) for 21 QuasiCertifProtocol-COL-18-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 22
[[35mlola[0m][I] fired transitions : 66
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 74 (type SKEL/SRCH) for QuasiCertifProtocol-COL-18-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 QuasiCertifProtocol-COL-18-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 22
[[35mlola[0m][I] fired transitions : 84
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 QuasiCertifProtocol-COL-18-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 4/257 3/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 323868 m, 64773 m/sec, 2042972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 9/257 5/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 693979 m, 74022 m/sec, 4569877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 14/257 8/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 1018431 m, 64890 m/sec, 7008548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 19/257 10/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 1306973 m, 57708 m/sec, 9465986 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 24/257 12/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 1677958 m, 74197 m/sec, 11981797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 29/257 15/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 2018782 m, 68164 m/sec, 14440045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 34/257 16/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 2291416 m, 54526 m/sec, 16850114 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 39/257 19/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 2653978 m, 72512 m/sec, 19367756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 44/257 21/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 2993949 m, 67994 m/sec, 21825747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 49/257 23/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 3258805 m, 52971 m/sec, 24220212 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 54/257 25/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 3616389 m, 71516 m/sec, 26711612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 59/257 28/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 3934475 m, 63617 m/sec, 29120382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 64/257 29/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 4210023 m, 55109 m/sec, 31542620 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 69/257 32/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 4554536 m, 68902 m/sec, 34006483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 74/257 33/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 4827060 m, 54504 m/sec, 36393112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 79/257 36/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 5151864 m, 64960 m/sec, 38841268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 84/257 38/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 5438992 m, 57425 m/sec, 41233467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 89/257 40/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 5744780 m, 61157 m/sec, 43668331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 94/257 41/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 6022063 m, 55456 m/sec, 46059179 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 99/257 43/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 6322121 m, 60011 m/sec, 48463315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 104/257 45/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 6584512 m, 52478 m/sec, 50848946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 109/257 47/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 6873216 m, 57740 m/sec, 53224674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 114/257 49/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 7144927 m, 54342 m/sec, 55586076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 119/257 50/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 7398973 m, 50809 m/sec, 57932293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 124/257 52/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 7647810 m, 49767 m/sec, 60247638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 129/257 54/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 7895674 m, 49572 m/sec, 62554325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 134/257 55/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 8138569 m, 48579 m/sec, 64832917 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 139/257 57/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 8373503 m, 46986 m/sec, 67173231 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 144/257 58/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 8578143 m, 40928 m/sec, 69504355 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 149/257 59/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 8780689 m, 40509 m/sec, 71834642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 154/257 60/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 8960860 m, 36034 m/sec, 74154088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 159/257 63/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 9348662 m, 77560 m/sec, 76680779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 164/257 66/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 9692860 m, 68839 m/sec, 79152139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 169/257 67/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 9979700 m, 57368 m/sec, 81549543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 174/257 70/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 10317741 m, 67608 m/sec, 84026480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 179/257 72/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 10661555 m, 68762 m/sec, 86495665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 184/257 74/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 10945457 m, 56780 m/sec, 88885586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 189/257 76/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 11275516 m, 66011 m/sec, 91352168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 194/257 79/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 11603089 m, 65514 m/sec, 93772167 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 199/257 80/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 11863952 m, 52172 m/sec, 96157196 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 204/257 83/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 12216822 m, 70574 m/sec, 98619608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 209/257 85/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 12503736 m, 57382 m/sec, 100996934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 214/257 87/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 12809626 m, 61178 m/sec, 103427453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 219/257 89/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 13114075 m, 60889 m/sec, 105818077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 224/257 91/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 13395735 m, 56332 m/sec, 108226127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 229/257 92/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 13693556 m, 59564 m/sec, 110605587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 234/257 94/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 13973907 m, 56070 m/sec, 112990682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 239/257 96/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 14244285 m, 54075 m/sec, 115352369 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 244/257 98/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 14535425 m, 58228 m/sec, 117715301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 249/257 100/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 14792080 m, 51331 m/sec, 120063534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 254/257 101/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 15043994 m, 50382 m/sec, 122401665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 16 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-05 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 48 QuasiCertifProtocol-COL-18-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 QuasiCertifProtocol-COL-18-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 3340 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 5/3340 3/5 QuasiCertifProtocol-COL-18-CTLFireability-2024-05 390536 m, -2930691 m/sec, 2519099 t fired, .
[[35mlola[0m][.] 49 CTL EXCL 5/256 2/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 205819 m, 41163 m/sec, 2525798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 16 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-05 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 10/238 3/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 395623 m, 37960 m/sec, 5005318 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 15/256 5/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 588069 m, 38489 m/sec, 7527132 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 20/256 6/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 778011 m, 37988 m/sec, 10028943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 25/256 7/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 951861 m, 34770 m/sec, 12472416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 30/256 8/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 1106540 m, 30935 m/sec, 14860121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 35/256 9/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 1231078 m, 24907 m/sec, 17181475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 40/256 11/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 1433580 m, 40500 m/sec, 19698037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 45/256 12/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 1623989 m, 38081 m/sec, 22185590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 50/256 13/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 1809529 m, 37108 m/sec, 24664498 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 55/256 14/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 1988128 m, 35719 m/sec, 27124526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 60/256 15/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 2151709 m, 32716 m/sec, 29520600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 65/256 16/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 2280869 m, 25832 m/sec, 31850098 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 70/256 18/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 2457776 m, 35381 m/sec, 34330552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 75/256 19/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 2649403 m, 38325 m/sec, 36840861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 80/256 20/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 2836168 m, 37353 m/sec, 39328874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 85/256 21/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 3008070 m, 34380 m/sec, 41755822 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 90/256 22/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 3160031 m, 30392 m/sec, 44108593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 95/256 23/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 3287228 m, 25439 m/sec, 46437534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 100/256 24/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 3478899 m, 38334 m/sec, 48946506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 105/256 26/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 3667807 m, 37781 m/sec, 51436357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 110/256 27/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 3841832 m, 34805 m/sec, 53871500 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 115/256 28/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 3997719 m, 31177 m/sec, 56246364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 120/256 29/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 4119445 m, 24345 m/sec, 58566909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 125/256 30/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 4309989 m, 38108 m/sec, 61080066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 130/256 31/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 4492905 m, 36583 m/sec, 63547156 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 135/256 32/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 4659105 m, 33240 m/sec, 65941202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 140/256 33/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 4799369 m, 28052 m/sec, 68284286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 145/256 34/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 4947697 m, 29665 m/sec, 70677986 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 150/256 36/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 5133504 m, 37161 m/sec, 73156648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 155/256 37/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 5298272 m, 32953 m/sec, 75547625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 160/256 38/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 5440406 m, 28426 m/sec, 77903072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 165/256 39/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 5585796 m, 29078 m/sec, 80281573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 170/256 40/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 5763722 m, 35585 m/sec, 82721102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 175/256 41/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 5926310 m, 32517 m/sec, 85100350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 180/256 42/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 6051025 m, 24943 m/sec, 87413315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 185/256 43/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 6219654 m, 33725 m/sec, 89841757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 190/256 44/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 6381935 m, 32456 m/sec, 92219871 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 195/256 45/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 6513627 m, 26338 m/sec, 94543272 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 200/256 46/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 6666394 m, 30553 m/sec, 96925713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 205/256 47/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 6828484 m, 32418 m/sec, 99293207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 210/256 48/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 6951146 m, 24532 m/sec, 101595570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 215/256 49/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 7109250 m, 31620 m/sec, 103963707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 220/256 49/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 7248984 m, 27946 m/sec, 106283678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 225/256 50/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 7385207 m, 27244 m/sec, 108588803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 230/256 51/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 7526231 m, 28204 m/sec, 110897419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 235/256 52/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 7655876 m, 25929 m/sec, 113189562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 240/256 53/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 7794712 m, 27767 m/sec, 115487023 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 245/256 54/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 7926636 m, 26384 m/sec, 117763833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 250/256 55/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 8048189 m, 24310 m/sec, 119992033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 255/256 55/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 8182783 m, 26918 m/sec, 122288239 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 49 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 QuasiCertifProtocol-COL-18-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 48 QuasiCertifProtocol-COL-18-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 3080 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 5/256 3/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 377715 m, 75543 m/sec, 2445259 t fired, .
[[35mlola[0m][.] 49 CTL EXCL 5/3080 2/5 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 208829 m, -1594790 m/sec, 2564084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 10/256 6/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 733053 m, 71067 m/sec, 4854151 t fired, .
[[35mlola[0m][.] 49 CTL EXCL 10/236 3/5 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 403566 m, 38947 m/sec, 5098752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 15/256 8/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 1038958 m, 61181 m/sec, 7162175 t fired, .
[[35mlola[0m][.] 49 CTL EXCL 15/236 5/5 QuasiCertifProtocol-COL-18-CTLFireability-2024-12 596777 m, 38642 m/sec, 7629316 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 49 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 20/256 10/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 1315135 m, 55235 m/sec, 9518929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 25/256 12/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 1685125 m, 73998 m/sec, 12025016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 30/256 15/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 2023610 m, 67697 m/sec, 14470399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 35/256 16/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 2291970 m, 53672 m/sec, 16856570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 40/256 19/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 2650985 m, 71803 m/sec, 19350517 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 45/256 21/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 2988233 m, 67449 m/sec, 21790420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 50/256 23/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 3254317 m, 53216 m/sec, 24166242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 55/256 25/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 3608596 m, 70855 m/sec, 26647821 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 60/256 27/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 3926450 m, 63570 m/sec, 29051659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 65/256 29/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 4196146 m, 53939 m/sec, 31427353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 70/256 32/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 4530553 m, 66881 m/sec, 33816165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 75/256 33/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 4802742 m, 54437 m/sec, 36130863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 80/256 35/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 5115934 m, 62638 m/sec, 38559586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 85/256 37/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 5409667 m, 58746 m/sec, 40940920 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 90/256 39/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 5701892 m, 58445 m/sec, 43350716 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 95/256 41/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 5986513 m, 56924 m/sec, 45722535 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 100/256 43/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 6273170 m, 57331 m/sec, 48071529 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 105/256 45/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 6528638 m, 51093 m/sec, 50364910 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 110/256 47/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 6820059 m, 58284 m/sec, 52699611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 115/256 48/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 7071620 m, 50312 m/sec, 55004056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 120/256 50/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 7315780 m, 48832 m/sec, 57288825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 125/256 52/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 7576768 m, 52197 m/sec, 59559896 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 130/256 53/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 7820540 m, 48754 m/sec, 61814676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 135/256 55/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 8047297 m, 45351 m/sec, 64009584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 140/256 56/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 8278920 m, 46324 m/sec, 66273438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 145/256 58/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 8506913 m, 45598 m/sec, 68656625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 150/256 59/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 8703539 m, 39325 m/sec, 70943340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 155/256 60/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 8889949 m, 37282 m/sec, 73204203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 160/256 62/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 9184283 m, 58866 m/sec, 75593108 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 165/256 65/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 9540813 m, 71306 m/sec, 78027886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 170/256 67/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 9852106 m, 62258 m/sec, 80372685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 175/256 68/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 10127285 m, 55035 m/sec, 82741381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 180/256 71/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 10483207 m, 71184 m/sec, 85179322 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 185/256 73/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 10793766 m, 62111 m/sec, 87533402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 190/256 75/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 11064853 m, 54217 m/sec, 89896498 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 195/256 77/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 11412917 m, 69612 m/sec, 92318587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 200/256 79/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 11713716 m, 60159 m/sec, 94656483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 205/256 81/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 11995783 m, 56413 m/sec, 97030132 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 210/256 83/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 12319331 m, 64709 m/sec, 99402486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 215/256 85/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 12575417 m, 51217 m/sec, 101724155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 220/256 87/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 12902041 m, 65324 m/sec, 104111627 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 225/256 89/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 13176334 m, 54858 m/sec, 106432765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 230/256 91/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 13473597 m, 59452 m/sec, 108791628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 235/256 93/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 13744369 m, 54154 m/sec, 111106642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 240/256 95/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 14031065 m, 57339 m/sec, 113442675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 245/256 96/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 14278775 m, 49542 m/sec, 115748746 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 250/256 98/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 14573524 m, 58949 m/sec, 118059290 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 255/256 100/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 14829234 m, 51142 m/sec, 120354551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 46 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 QuasiCertifProtocol-COL-18-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 QuasiCertifProtocol-COL-18-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 2820 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 5/256 3/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 365522 m, 73104 m/sec, 2331706 t fired, .
[[35mlola[0m][.] 46 CTL EXCL 5/2820 3/5 QuasiCertifProtocol-COL-18-CTLFireability-2024-11 377501 m, -2890346 m/sec, 2442808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 46 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 10/256 5/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 641325 m, 55160 m/sec, 4189764 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 15/256 7/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 965333 m, 64801 m/sec, 6577213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 20/256 9/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 1219676 m, 50868 m/sec, 8925589 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 25/256 12/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 1589695 m, 74003 m/sec, 11377504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 30/256 14/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 1932582 m, 68577 m/sec, 13765990 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 35/256 16/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 2215317 m, 56547 m/sec, 16081170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 40/256 18/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 2521336 m, 61203 m/sec, 18464175 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 45/256 20/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 2867036 m, 69140 m/sec, 20894049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 50/256 22/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 3167394 m, 60071 m/sec, 23276693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 55/256 24/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 3470090 m, 60539 m/sec, 25716685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 60/256 27/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 3813865 m, 68755 m/sec, 28173370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 65/256 28/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 4086383 m, 54503 m/sec, 30563154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 70/256 31/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 4424712 m, 67665 m/sec, 33028745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 75/256 33/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 4728982 m, 60854 m/sec, 35399979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 80/256 35/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 5014162 m, 57036 m/sec, 37828058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 85/256 37/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 5332457 m, 63659 m/sec, 40238935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 90/256 39/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 5606599 m, 54828 m/sec, 42658523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 95/256 41/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 5920291 m, 62738 m/sec, 45062208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 100/256 43/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 6190635 m, 54068 m/sec, 47457440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 105/256 44/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 6474124 m, 56697 m/sec, 49814983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 110/256 46/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 6752060 m, 55587 m/sec, 52159882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 115/256 48/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 7007721 m, 51132 m/sec, 54499447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 120/256 50/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 7274890 m, 53433 m/sec, 56815456 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 125/256 51/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 7530798 m, 51181 m/sec, 59120821 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 130/256 53/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 7779862 m, 49812 m/sec, 61431179 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 135/256 54/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 8018252 m, 47678 m/sec, 63694422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 140/256 56/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 8253837 m, 47117 m/sec, 65986084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 145/256 57/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 8476453 m, 44523 m/sec, 68307667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 150/256 59/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 8670367 m, 38782 m/sec, 70565962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 155/256 60/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 8859109 m, 37748 m/sec, 72814888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 160/256 62/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 9118464 m, 51871 m/sec, 75155170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 165/256 64/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 9487885 m, 73884 m/sec, 77674533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 170/256 67/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 9831739 m, 68770 m/sec, 80228411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 175/256 69/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 10132228 m, 60097 m/sec, 82781898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 180/256 71/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 10512280 m, 76010 m/sec, 85406469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 185/256 73/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 10846666 m, 66877 m/sec, 87944911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 190/256 75/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 11143869 m, 59440 m/sec, 90442605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 195/256 78/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 11488137 m, 68853 m/sec, 92885527 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 200/256 80/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 11773510 m, 57074 m/sec, 95260564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 205/256 82/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 12088797 m, 63057 m/sec, 97694682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 210/256 84/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 12403701 m, 62980 m/sec, 100073477 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 215/256 86/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 12671886 m, 53637 m/sec, 102461913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 220/256 88/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 13000098 m, 65642 m/sec, 104868920 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 225/256 90/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 13258088 m, 51598 m/sec, 107233542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 230/256 92/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 13578996 m, 64181 m/sec, 109621605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 235/256 93/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 13841534 m, 52507 m/sec, 111991828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 240/256 95/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 14145478 m, 60788 m/sec, 114357191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 245/256 97/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 14411723 m, 53249 m/sec, 116723966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 250/256 99/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 14672747 m, 52204 m/sec, 119061575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 255/256 101/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 14948811 m, 55212 m/sec, 121397881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 33 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-08 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 21 QuasiCertifProtocol-COL-18-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 QuasiCertifProtocol-COL-18-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 2560 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 21
[[35mlola[0m][I] fired transitions : 20
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 5/284 3/5 QuasiCertifProtocol-COL-18-CTLFireability-2024-08 391669 m, -2911428 m/sec, 2524305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 33 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-08 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 QuasiCertifProtocol-COL-18-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 318 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 5/318 3/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 354876 m, 70975 m/sec, 2600686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 10/318 5/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 680153 m, 65055 m/sec, 5166300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 15/318 7/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 970231 m, 58015 m/sec, 7591928 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 20/318 9/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 1206715 m, 47296 m/sec, 9975172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 25/318 11/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 1529220 m, 64501 m/sec, 12469560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 30/318 13/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 1837852 m, 61726 m/sec, 14943336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 35/318 15/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 2118923 m, 56214 m/sec, 17333190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 40/318 17/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 2358672 m, 47949 m/sec, 19732474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 45/318 19/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 2681392 m, 64544 m/sec, 22219365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 50/318 21/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 2973100 m, 58341 m/sec, 24656985 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 55/318 23/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 3221543 m, 49688 m/sec, 27031643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 60/318 25/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 3511635 m, 58018 m/sec, 29490279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 65/318 27/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 3806469 m, 58966 m/sec, 31918994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 70/318 28/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 4054177 m, 49541 m/sec, 34283363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 75/318 30/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 4333411 m, 55846 m/sec, 36714513 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 80/318 32/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 4616926 m, 56703 m/sec, 39114276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 85/318 34/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 4848211 m, 46257 m/sec, 41472304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 90/318 36/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 5143154 m, 58988 m/sec, 43905014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 95/318 37/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 5402604 m, 51890 m/sec, 46265460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 100/318 39/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 5652188 m, 49916 m/sec, 48656501 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 105/318 41/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 5924118 m, 54386 m/sec, 51017654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 110/318 42/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 6160809 m, 47338 m/sec, 53385226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 115/318 44/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 6423867 m, 52611 m/sec, 55728758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 120/318 46/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 6658811 m, 46988 m/sec, 58084847 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 125/318 47/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 6903309 m, 48899 m/sec, 60415394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 130/318 49/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 7145722 m, 48482 m/sec, 62739977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 135/318 50/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 7369401 m, 44735 m/sec, 65069130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 140/318 52/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 7596624 m, 45444 m/sec, 67370207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 145/318 53/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 7821874 m, 45050 m/sec, 69650470 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 150/318 55/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 8032754 m, 42176 m/sec, 71880881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 155/318 56/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 8247302 m, 42909 m/sec, 74163666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 160/318 57/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 8451494 m, 40838 m/sec, 76456976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 165/318 58/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 8625976 m, 34896 m/sec, 78740210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 170/318 59/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 8810355 m, 36875 m/sec, 81018872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 175/318 61/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 8993499 m, 36628 m/sec, 83334633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 180/318 63/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 9317863 m, 64872 m/sec, 85817171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 185/318 65/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 9624273 m, 61282 m/sec, 88268004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 190/318 67/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 9897196 m, 54584 m/sec, 90639735 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 195/318 69/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 10146142 m, 49789 m/sec, 93041688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 200/318 71/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 10462615 m, 63294 m/sec, 95513828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 205/318 73/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 10748833 m, 57243 m/sec, 97916374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 210/318 74/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 10983292 m, 46891 m/sec, 100273519 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 215/318 76/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 11285911 m, 60523 m/sec, 102730769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 220/318 78/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 11578022 m, 58422 m/sec, 105141342 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 225/318 80/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 11814609 m, 47317 m/sec, 107491403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 230/318 82/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 12102256 m, 57529 m/sec, 109908431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 235/318 84/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 12381575 m, 55863 m/sec, 112297166 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 240/318 85/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 12620548 m, 47794 m/sec, 114710201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 245/318 87/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 12920098 m, 59910 m/sec, 117168058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 250/318 89/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 13170288 m, 50038 m/sec, 119552814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 255/318 91/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 13438450 m, 53632 m/sec, 121980386 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 260/318 92/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 13699419 m, 52193 m/sec, 124371284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 265/318 94/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 13953844 m, 50885 m/sec, 126777772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 270/318 96/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 14202129 m, 49657 m/sec, 129132536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 275/318 97/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 14454096 m, 50393 m/sec, 131512520 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 280/318 99/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 14682204 m, 45621 m/sec, 133858748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 285/318 101/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 14937680 m, 51095 m/sec, 136216067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 290/318 102/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 15170180 m, 46500 m/sec, 138563090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 295/318 104/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 15392369 m, 44437 m/sec, 140889679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 300/318 105/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 15613641 m, 44254 m/sec, 143202200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 305/318 106/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 15827567 m, 42785 m/sec, 145460744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 310/318 108/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 16047500 m, 43986 m/sec, 147788625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 315/318 109/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 16243318 m, 39163 m/sec, 150106715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 19 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-06 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 QuasiCertifProtocol-COL-18-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 318 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 QuasiCertifProtocol-COL-18-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 2230 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 5/318 3/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 383590 m, 76718 m/sec, 2477457 t fired, .
[[35mlola[0m][.] 19 CTL EXCL 5/2230 3/5 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 348024 m, -3179058 m/sec, 2539122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 10/318 6/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 740539 m, 71389 m/sec, 4924600 t fired, .
[[35mlola[0m][.] 19 CTL EXCL 10/278 5/5 QuasiCertifProtocol-COL-18-CTLFireability-2024-06 664043 m, 63203 m/sec, 5053090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 19 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-06 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 15/318 8/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 1056496 m, 63191 m/sec, 7314268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 20/318 10/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 1343029 m, 57306 m/sec, 9738037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 25/318 13/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 1717890 m, 74972 m/sec, 12226630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 30/318 15/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 2047182 m, 65858 m/sec, 14647699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 35/318 16/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 2305073 m, 51578 m/sec, 17012976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 40/318 19/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 2674345 m, 73854 m/sec, 19493096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 45/318 21/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 3003961 m, 65923 m/sec, 21908048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 50/318 23/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 3262821 m, 51772 m/sec, 24268708 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 55/318 25/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 3618204 m, 71076 m/sec, 26727638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 60/318 28/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 3933234 m, 63006 m/sec, 29107907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 65/318 29/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 4204990 m, 54351 m/sec, 31498523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 70/318 32/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 4543921 m, 67786 m/sec, 33919513 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 75/318 33/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 4816185 m, 54452 m/sec, 36270304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 80/318 36/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 5133297 m, 63422 m/sec, 38682352 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 85/318 37/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 5418129 m, 56966 m/sec, 41033198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 90/318 39/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 5709298 m, 58233 m/sec, 43415541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 95/318 41/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 5991621 m, 56464 m/sec, 45763043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 100/318 43/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 6280036 m, 57683 m/sec, 48128829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 105/318 45/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 6536896 m, 51372 m/sec, 50464588 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 110/318 47/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 6831714 m, 58963 m/sec, 52803107 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 115/318 48/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 7088911 m, 51439 m/sec, 55134970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 120/318 50/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 7339227 m, 50063 m/sec, 57451218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 125/318 52/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 7594678 m, 51090 m/sec, 59748691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 130/318 53/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 7840953 m, 49255 m/sec, 62034948 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 135/318 55/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 8068791 m, 45567 m/sec, 64259259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 140/318 56/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 8314011 m, 49044 m/sec, 66571024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 145/318 58/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 8524811 m, 42160 m/sec, 68861831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 150/318 59/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 8724638 m, 39965 m/sec, 71152955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 155/318 60/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 8906329 m, 36338 m/sec, 73438675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 160/318 62/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 9225543 m, 63842 m/sec, 75865832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 165/318 65/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 9580196 m, 70930 m/sec, 78312769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 170/318 67/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 9888521 m, 61665 m/sec, 80674534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 175/318 69/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 10170673 m, 56430 m/sec, 83069639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 180/318 71/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 10526504 m, 71166 m/sec, 85517999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 185/318 73/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 10838945 m, 62488 m/sec, 87885991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 190/318 75/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 11115673 m, 55345 m/sec, 90279194 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 195/318 78/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 11466870 m, 70239 m/sec, 92710950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 200/318 80/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 11752966 m, 57219 m/sec, 95055148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 205/318 82/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 12047960 m, 58998 m/sec, 97418787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 210/318 84/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 12364431 m, 63294 m/sec, 99765149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 215/318 85/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 12621772 m, 51468 m/sec, 102098545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 220/318 88/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 12948678 m, 65381 m/sec, 104472943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 225/318 89/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 13210363 m, 52337 m/sec, 106793983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1595 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 230/318 91/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 13520545 m, 62036 m/sec, 109152868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1600 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 235/318 93/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 13777554 m, 51401 m/sec, 111466453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1605 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 240/318 95/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 14075268 m, 59542 m/sec, 113789384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1610 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 245/318 97/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 14329961 m, 50938 m/sec, 116107754 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1615 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 250/318 98/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 14606859 m, 55379 m/sec, 118404554 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1620 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 255/318 100/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 14872647 m, 53157 m/sec, 120699255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1625 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 260/318 102/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 15118687 m, 49208 m/sec, 122980064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1630 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 265/318 103/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 15361218 m, 48506 m/sec, 125243236 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1635 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 270/318 105/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 15599886 m, 47733 m/sec, 127489574 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1640 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 275/318 106/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 15840097 m, 48042 m/sec, 129737798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 280/318 108/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 16077806 m, 47541 m/sec, 132042653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1650 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 285/318 109/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 16284503 m, 41339 m/sec, 134342873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1655 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 290/318 111/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 16486784 m, 40456 m/sec, 136650685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1660 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 295/318 112/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 16660783 m, 34799 m/sec, 138900418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1665 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 300/318 114/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 16994047 m, 66652 m/sec, 141307505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1670 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 305/318 116/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 17337737 m, 68738 m/sec, 143763224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1675 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 310/318 118/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 17607039 m, 53860 m/sec, 146110596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1680 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 315/318 120/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 17942437 m, 67079 m/sec, 148553204 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1685 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 13 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-04 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1690 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 QuasiCertifProtocol-COL-18-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 318 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 QuasiCertifProtocol-COL-18-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 1910 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 255
[[35mlola[0m][I] fired transitions : 264
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 5/318 3/5 QuasiCertifProtocol-COL-18-CTLFireability-2024-04 381793 m, -3512128 m/sec, 2468994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1695 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 13 (type EXCL) for QuasiCertifProtocol-COL-18-CTLFireability-2024-04 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1700 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 QuasiCertifProtocol-COL-18-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 380 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 5/380 3/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 310544 m, 62108 m/sec, 2583621 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1705 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 10/380 5/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 601909 m, 58273 m/sec, 5138749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1710 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 15/380 7/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 874509 m, 54520 m/sec, 7647502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1715 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 20/380 8/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 1118076 m, 48713 m/sec, 10094452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1720 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 25/380 10/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 1360954 m, 48575 m/sec, 12590841 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1725 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 30/380 12/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 1656718 m, 59152 m/sec, 15139807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1730 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 35/380 14/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 1934270 m, 55510 m/sec, 17649280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1735 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 40/380 16/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 2178018 m, 48749 m/sec, 20060746 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1740 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 45/380 17/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 2400818 m, 44560 m/sec, 22437975 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1745 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 50/380 19/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 2683564 m, 56549 m/sec, 24917984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1750 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 55/380 21/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 2950730 m, 53433 m/sec, 27396534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1755 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 60/380 22/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 3183234 m, 46500 m/sec, 29813073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1760 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 65/380 24/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 3431928 m, 49738 m/sec, 32287815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1765 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 70/380 26/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 3705130 m, 54640 m/sec, 34789729 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1770 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 75/380 28/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 3957050 m, 50384 m/sec, 37220083 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1775 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 80/380 29/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 4180351 m, 44660 m/sec, 39668909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1780 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 85/380 31/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 4453754 m, 54680 m/sec, 42175066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1785 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 90/380 33/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 4704899 m, 50229 m/sec, 44607016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1790 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 95/380 34/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 4926636 m, 44347 m/sec, 47053947 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1795 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 100/380 36/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 5194527 m, 53578 m/sec, 49539004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1800 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 105/380 37/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 5425122 m, 46119 m/sec, 51964750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1805 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 110/380 39/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 5665970 m, 48169 m/sec, 54427154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1810 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 115/380 41/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 5916005 m, 50007 m/sec, 56860632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1815 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 120/380 42/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 6132071 m, 43213 m/sec, 59293779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1820 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 125/380 44/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 6381742 m, 49934 m/sec, 61714283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1825 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 130/380 45/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 6595955 m, 42842 m/sec, 64136745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1830 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 135/380 47/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 6838826 m, 48574 m/sec, 66550950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1835 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 140/380 48/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 7053650 m, 42964 m/sec, 68959127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1840 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-07: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] QuasiCertifProtocol-COL-18-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 145/380 50/2000 QuasiCertifProtocol-COL-18-CTLFireability-2024-02 7273687 m, 44007 m/sec, 71351450 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1845 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mQuasiCertifProtocol-COL-18-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-10: DISJ true state space[0m
[[35mlola[0m][.] [1m[32mQuasiCertifProtocol-COL-18-CTLFireability-2024-13: EF true state space[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-COL-18"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is QuasiCertifProtocol-COL-18, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r313-tall-171662339600026"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-COL-18.tgz
mv QuasiCertifProtocol-COL-18 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;