About the Execution of LoLA for PolyORBLF-PT-S06J06T04
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16205.348 | 1037091.00 | 2149516.00 | 1400.70 | T????????FFT??F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r291-tajo-171654448100338.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PolyORBLF-PT-S06J06T04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r291-tajo-171654448100338
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 12M
-rw-r--r-- 1 mcc users 16K Apr 11 17:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 101K Apr 11 17:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 221K Apr 11 17:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 855K Apr 11 17:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 9.5K Apr 23 07:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 42K Apr 23 07:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 113K Apr 23 07:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 341K Apr 23 07:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 23K Apr 11 17:59 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Apr 11 17:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 483K Apr 11 17:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 2.1M Apr 11 17:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.2K Apr 23 07:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.8K Apr 23 07:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 6.9M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-00
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-01
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-02
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-03
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-04
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-05
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-06
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-07
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-08
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-09
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-10
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-11
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-12
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-13
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-14
FORMULA_NAME PolyORBLF-PT-S06J06T04-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717065658104
FORMULA PolyORBLF-PT-S06J06T04-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S06J06T04-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S06J06T04-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S06J06T04-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S06J06T04-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717066695195
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 12 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 PolyORBLF-PT-S06J06T04-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1356
[[35mlola[0m][I] fired transitions : 4433
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 30 PolyORBLF-PT-S06J06T04-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EQUN) for 39 PolyORBLF-PT-S06J06T04-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 55 (type EQUN) for 15 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 2 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 5/239 2/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 238324 m, 47664 m/sec, 682871 t fired, .
[[35mlola[0m][.] 55 EF STEQ 0/1791 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 58 EF STEQ 2/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 18 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 15 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type EQUN) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 10/239 8/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 910060 m, 134347 m/sec, 2303389 t fired, .
[[35mlola[0m][.] 55 EF STEQ 5/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 5/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 23 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 15/239 14/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 1603112 m, 138610 m/sec, 3909939 t fired, .
[[35mlola[0m][.] 55 EF STEQ 10/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 10/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 28 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 20/239 19/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 2294005 m, 138178 m/sec, 5494896 t fired, .
[[35mlola[0m][.] 55 EF STEQ 15/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 15/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 33 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 25/239 24/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 2978572 m, 136913 m/sec, 7073718 t fired, .
[[35mlola[0m][.] 55 EF STEQ 20/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 20/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 38 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 30/239 29/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 3656197 m, 135525 m/sec, 8633217 t fired, .
[[35mlola[0m][.] 55 EF STEQ 25/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 25/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 43 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 35/239 34/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 4261285 m, 121017 m/sec, 10027063 t fired, .
[[35mlola[0m][.] 55 EF STEQ 30/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 30/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 48 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 40/239 39/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 4848638 m, 117470 m/sec, 11375500 t fired, .
[[35mlola[0m][.] 55 EF STEQ 35/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 35/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 53 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 45/239 43/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 5460124 m, 122297 m/sec, 12780476 t fired, .
[[35mlola[0m][.] 55 EF STEQ 40/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 40/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 58 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 50/239 48/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 6081262 m, 124227 m/sec, 14216272 t fired, .
[[35mlola[0m][.] 55 EF STEQ 45/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 45/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 63 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 55/239 53/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 6743414 m, 132430 m/sec, 15739376 t fired, .
[[35mlola[0m][.] 55 EF STEQ 50/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 50/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 68 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 60/239 58/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 7410603 m, 133437 m/sec, 17277189 t fired, .
[[35mlola[0m][.] 55 EF STEQ 55/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 55/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 73 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 65/239 63/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 8086423 m, 135164 m/sec, 18834051 t fired, .
[[35mlola[0m][.] 55 EF STEQ 60/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 60/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 78 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 70/239 68/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 8761836 m, 135082 m/sec, 20395001 t fired, .
[[35mlola[0m][.] 55 EF STEQ 65/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 65/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 83 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 75/239 73/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 9436704 m, 134973 m/sec, 21950071 t fired, .
[[35mlola[0m][.] 55 EF STEQ 70/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 70/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 88 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 80/239 78/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 10110490 m, 134757 m/sec, 23509515 t fired, .
[[35mlola[0m][.] 55 EF STEQ 75/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 75/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 93 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 85/239 83/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 10779551 m, 133812 m/sec, 25053188 t fired, .
[[35mlola[0m][.] 55 EF STEQ 80/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 80/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 98 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 90/239 88/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 11446469 m, 133383 m/sec, 26597223 t fired, .
[[35mlola[0m][.] 55 EF STEQ 85/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 85/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 103 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 95/239 93/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 12110526 m, 132811 m/sec, 28132485 t fired, .
[[35mlola[0m][.] 55 EF STEQ 90/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 90/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 108 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 100/239 98/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 12773733 m, 132641 m/sec, 29672389 t fired, .
[[35mlola[0m][.] 55 EF STEQ 95/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 95/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 113 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 105/239 103/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 13433536 m, 131960 m/sec, 31205333 t fired, .
[[35mlola[0m][.] 55 EF STEQ 100/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 100/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 118 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 2 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 110/239 108/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 14091360 m, 131564 m/sec, 32738041 t fired, .
[[35mlola[0m][.] 55 EF STEQ 105/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 62 EF STEQ 105/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 123 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 55 (type EQUN) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 115/239 112/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 14752534 m, 132234 m/sec, 34274336 t fired, .
[[35mlola[0m][.] 62 EF STEQ 110/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 128 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 120/239 117/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 15411116 m, 131716 m/sec, 35799381 t fired, .
[[35mlola[0m][.] 62 EF STEQ 115/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 133 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 125/239 122/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 16063991 m, 130575 m/sec, 37319876 t fired, .
[[35mlola[0m][.] 62 EF STEQ 120/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 138 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 130/239 127/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 16698780 m, 126957 m/sec, 38789907 t fired, .
[[35mlola[0m][.] 62 EF STEQ 125/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 143 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 135/239 131/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 17271268 m, 114497 m/sec, 40121674 t fired, .
[[35mlola[0m][.] 62 EF STEQ 130/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 148 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 140/239 135/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 17842669 m, 114280 m/sec, 41441588 t fired, .
[[35mlola[0m][.] 62 EF STEQ 135/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 153 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 145/239 139/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 18375230 m, 106512 m/sec, 42675486 t fired, .
[[35mlola[0m][.] 62 EF STEQ 140/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 158 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 150/239 143/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 18954455 m, 115845 m/sec, 44025193 t fired, .
[[35mlola[0m][.] 62 EF STEQ 145/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 163 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 155/239 148/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 19549390 m, 118987 m/sec, 45399963 t fired, .
[[35mlola[0m][.] 62 EF STEQ 150/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 168 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 160/239 152/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 20144173 m, 118956 m/sec, 46772882 t fired, .
[[35mlola[0m][.] 62 EF STEQ 155/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 173 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 165/239 156/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 20694657 m, 110096 m/sec, 48046179 t fired, .
[[35mlola[0m][.] 62 EF STEQ 160/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 178 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 170/239 160/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 21242013 m, 109471 m/sec, 49318454 t fired, .
[[35mlola[0m][.] 62 EF STEQ 165/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 183 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 175/239 164/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 21785929 m, 108783 m/sec, 50582375 t fired, .
[[35mlola[0m][.] 62 EF STEQ 170/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 188 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 180/239 168/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 22335115 m, 109837 m/sec, 51858620 t fired, .
[[35mlola[0m][.] 62 EF STEQ 175/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 193 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 185/239 172/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 22915630 m, 116103 m/sec, 53201724 t fired, .
[[35mlola[0m][.] 62 EF STEQ 180/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 198 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 190/239 176/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 23470954 m, 111064 m/sec, 54492971 t fired, .
[[35mlola[0m][.] 62 EF STEQ 185/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 203 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 195/239 180/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 24004742 m, 106757 m/sec, 55730983 t fired, .
[[35mlola[0m][.] 62 EF STEQ 190/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 208 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 200/239 184/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 24555693 m, 110190 m/sec, 57009836 t fired, .
[[35mlola[0m][.] 62 EF STEQ 195/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 213 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 205/239 188/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 25131511 m, 115163 m/sec, 58397366 t fired, .
[[35mlola[0m][.] 62 EF STEQ 200/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 218 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 210/239 192/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 25705284 m, 114754 m/sec, 59730161 t fired, .
[[35mlola[0m][.] 62 EF STEQ 205/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 223 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 215/239 197/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 26324879 m, 123919 m/sec, 61163983 t fired, .
[[35mlola[0m][.] 62 EF STEQ 210/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 228 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 220/239 201/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 26955930 m, 126210 m/sec, 62622687 t fired, .
[[35mlola[0m][.] 62 EF STEQ 215/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 233 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 225/239 206/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 27580571 m, 124928 m/sec, 64071925 t fired, .
[[35mlola[0m][.] 62 EF STEQ 220/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 238 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 230/239 210/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 28172814 m, 118448 m/sec, 65456717 t fired, .
[[35mlola[0m][.] 62 EF STEQ 225/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 243 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 235/239 215/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 28795827 m, 124602 m/sec, 66913305 t fired, .
[[35mlola[0m][.] 62 EF STEQ 230/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 248 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EF STEQ 235/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 253 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 30 PolyORBLF-PT-S06J06T04-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 PolyORBLF-PT-S06J06T04-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 3347 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2992
[[35mlola[0m][I] fired transitions : 3922
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 7 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EF STEQ 240/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 258 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 5/257 4/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 380863 m, 76172 m/sec, 1938539 t fired, .
[[35mlola[0m][.] 62 EF STEQ 245/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 263 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 10/257 7/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 774908 m, 78809 m/sec, 3830261 t fired, .
[[35mlola[0m][.] 62 EF STEQ 250/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 268 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 15/257 10/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 1170085 m, 79035 m/sec, 5705750 t fired, .
[[35mlola[0m][.] 62 EF STEQ 255/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 273 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 20/257 14/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 1563729 m, 78728 m/sec, 7560895 t fired, .
[[35mlola[0m][.] 62 EF STEQ 260/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 278 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 25/257 17/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 1955174 m, 78289 m/sec, 9402400 t fired, .
[[35mlola[0m][.] 62 EF STEQ 265/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 283 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 30/257 20/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 2346172 m, 78199 m/sec, 11237908 t fired, .
[[35mlola[0m][.] 62 EF STEQ 270/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 288 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 35/257 23/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 2691307 m, 69027 m/sec, 12857462 t fired, .
[[35mlola[0m][.] 62 EF STEQ 275/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 293 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 40/257 26/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 3075884 m, 76915 m/sec, 14667014 t fired, .
[[35mlola[0m][.] 62 EF STEQ 280/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 298 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 45/257 29/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 3414336 m, 67690 m/sec, 16291026 t fired, .
[[35mlola[0m][.] 62 EF STEQ 285/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 303 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 50/257 31/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 3677924 m, 52717 m/sec, 17545252 t fired, .
[[35mlola[0m][.] 62 EF STEQ 290/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 308 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 55/257 34/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 4032589 m, 70933 m/sec, 19232549 t fired, .
[[35mlola[0m][.] 62 EF STEQ 295/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 313 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 60/257 37/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 4395476 m, 72577 m/sec, 20972249 t fired, .
[[35mlola[0m][.] 62 EF STEQ 300/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 318 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 65/257 40/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 4750973 m, 71099 m/sec, 22683131 t fired, .
[[35mlola[0m][.] 62 EF STEQ 305/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 323 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 70/257 43/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 5115685 m, 72942 m/sec, 24421441 t fired, .
[[35mlola[0m][.] 62 EF STEQ 310/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 328 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 75/257 46/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 5483186 m, 73500 m/sec, 26198941 t fired, .
[[35mlola[0m][.] 62 EF STEQ 315/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 333 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 80/257 49/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 5832479 m, 69858 m/sec, 27897427 t fired, .
[[35mlola[0m][.] 62 EF STEQ 320/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 338 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 85/257 52/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 6198510 m, 73206 m/sec, 29668398 t fired, .
[[35mlola[0m][.] 62 EF STEQ 325/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 343 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 90/257 55/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 6551706 m, 70639 m/sec, 31392389 t fired, .
[[35mlola[0m][.] 62 EF STEQ 330/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 348 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 95/257 58/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 6908946 m, 71448 m/sec, 33139525 t fired, .
[[35mlola[0m][.] 62 EF STEQ 335/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 353 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 100/257 60/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 7223770 m, 62964 m/sec, 34672041 t fired, .
[[35mlola[0m][.] 62 EF STEQ 340/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 358 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 105/257 63/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 7545097 m, 64265 m/sec, 36247577 t fired, .
[[35mlola[0m][.] 62 EF STEQ 345/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 363 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 110/257 65/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 7870702 m, 65121 m/sec, 37842145 t fired, .
[[35mlola[0m][.] 62 EF STEQ 350/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 368 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 115/257 68/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 8198774 m, 65614 m/sec, 39430549 t fired, .
[[35mlola[0m][.] 62 EF STEQ 355/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 373 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 120/257 70/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 8505637 m, 61372 m/sec, 40920698 t fired, .
[[35mlola[0m][.] 62 EF STEQ 360/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 378 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 125/257 73/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 8823938 m, 63660 m/sec, 42485674 t fired, .
[[35mlola[0m][.] 62 EF STEQ 365/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 383 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 130/257 76/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 9148303 m, 64873 m/sec, 44094486 t fired, .
[[35mlola[0m][.] 62 EF STEQ 370/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 388 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 135/257 78/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 9494605 m, 69260 m/sec, 45791478 t fired, .
[[35mlola[0m][.] 62 EF STEQ 375/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 393 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 140/257 81/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 9842623 m, 69603 m/sec, 47514041 t fired, .
[[35mlola[0m][.] 62 EF STEQ 380/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 398 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 145/257 84/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 10194674 m, 70410 m/sec, 49241919 t fired, .
[[35mlola[0m][.] 62 EF STEQ 385/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 403 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 150/257 87/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 10546196 m, 70304 m/sec, 50964039 t fired, .
[[35mlola[0m][.] 62 EF STEQ 390/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 408 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 155/257 90/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 10898498 m, 70460 m/sec, 52688820 t fired, .
[[35mlola[0m][.] 62 EF STEQ 395/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 413 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 160/257 92/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 11251872 m, 70674 m/sec, 54410736 t fired, .
[[35mlola[0m][.] 62 EF STEQ 400/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 418 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 165/257 95/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 11604537 m, 70533 m/sec, 56130797 t fired, .
[[35mlola[0m][.] 62 EF STEQ 405/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 423 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 170/257 98/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 11945604 m, 68213 m/sec, 57860755 t fired, .
[[35mlola[0m][.] 62 EF STEQ 410/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 428 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 175/257 101/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 12296689 m, 70217 m/sec, 59583003 t fired, .
[[35mlola[0m][.] 62 EF STEQ 415/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 433 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 180/257 104/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 12647698 m, 70201 m/sec, 61302004 t fired, .
[[35mlola[0m][.] 62 EF STEQ 420/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 438 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 185/257 106/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 12996971 m, 69854 m/sec, 63022102 t fired, .
[[35mlola[0m][.] 62 EF STEQ 425/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 443 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 190/257 109/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 13343778 m, 69361 m/sec, 64740372 t fired, .
[[35mlola[0m][.] 62 EF STEQ 430/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 448 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 195/257 112/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 13659137 m, 63071 m/sec, 66293877 t fired, .
[[35mlola[0m][.] 62 EF STEQ 435/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 453 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 200/257 114/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 13960800 m, 60332 m/sec, 67813067 t fired, .
[[35mlola[0m][.] 62 EF STEQ 440/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 458 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 205/257 117/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 14303206 m, 68481 m/sec, 69535573 t fired, .
[[35mlola[0m][.] 62 EF STEQ 445/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 463 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 210/257 119/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 14620388 m, 63436 m/sec, 71122543 t fired, .
[[35mlola[0m][.] 62 EF STEQ 450/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 468 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 215/257 121/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 14861153 m, 48153 m/sec, 72299552 t fired, .
[[35mlola[0m][.] 62 EF STEQ 455/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 473 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 220/257 124/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 15165430 m, 60855 m/sec, 73814977 t fired, .
[[35mlola[0m][.] 62 EF STEQ 460/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 478 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 225/257 126/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 15484932 m, 63900 m/sec, 75415375 t fired, .
[[35mlola[0m][.] 62 EF STEQ 465/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 483 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 230/257 129/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 15815208 m, 66055 m/sec, 77039110 t fired, .
[[35mlola[0m][.] 62 EF STEQ 470/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 488 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 235/257 131/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 16128825 m, 62723 m/sec, 78611432 t fired, .
[[35mlola[0m][.] 62 EF STEQ 475/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 493 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 240/257 134/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 16443598 m, 62954 m/sec, 80143958 t fired, .
[[35mlola[0m][.] 62 EF STEQ 480/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 498 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 245/257 136/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 16777506 m, 66781 m/sec, 81778670 t fired, .
[[35mlola[0m][.] 62 EF STEQ 485/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 503 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 250/257 138/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 16971072 m, 38713 m/sec, 82737427 t fired, .
[[35mlola[0m][.] 62 EF STEQ 490/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 508 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 255/257 140/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 17290684 m, 63922 m/sec, 84334217 t fired, .
[[35mlola[0m][.] 62 EF STEQ 495/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 513 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 46 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EF STEQ 500/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 518 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 PolyORBLF-PT-S06J06T04-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 3082 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 197
[[35mlola[0m][I] fired transitions : 394
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 5/256 4/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 357999 m, -3386537 m/sec, 1828516 t fired, .
[[35mlola[0m][.] 62 EF STEQ 505/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 523 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 46 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EF STEQ 510/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 528 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 279 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 5/279 3/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 310750 m, 62150 m/sec, 1721274 t fired, .
[[35mlola[0m][.] 62 EF STEQ 515/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 533 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 10/279 6/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 655591 m, 68968 m/sec, 3465597 t fired, .
[[35mlola[0m][.] 62 EF STEQ 520/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 538 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 15/279 9/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 1002396 m, 69361 m/sec, 5194724 t fired, .
[[35mlola[0m][.] 62 EF STEQ 525/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 543 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 20/279 12/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 1346350 m, 68790 m/sec, 6910921 t fired, .
[[35mlola[0m][.] 62 EF STEQ 530/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 548 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 25/279 15/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 1690864 m, 68902 m/sec, 8604810 t fired, .
[[35mlola[0m][.] 62 EF STEQ 535/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 553 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 30/279 18/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 2030859 m, 67999 m/sec, 10292341 t fired, .
[[35mlola[0m][.] 62 EF STEQ 540/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 558 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 35/279 21/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 2370651 m, 67958 m/sec, 11986928 t fired, .
[[35mlola[0m][.] 62 EF STEQ 545/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 563 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 40/279 24/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 2712943 m, 68458 m/sec, 13681808 t fired, .
[[35mlola[0m][.] 62 EF STEQ 550/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 568 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 45/279 27/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 3050513 m, 67514 m/sec, 15370350 t fired, .
[[35mlola[0m][.] 62 EF STEQ 555/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 573 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 50/279 29/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 3372777 m, 64452 m/sec, 16965800 t fired, .
[[35mlola[0m][.] 62 EF STEQ 560/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 578 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 55/279 32/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 3677255 m, 60895 m/sec, 18504499 t fired, .
[[35mlola[0m][.] 62 EF STEQ 565/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 583 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 60/279 34/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 3967170 m, 57983 m/sec, 20004187 t fired, .
[[35mlola[0m][.] 62 EF STEQ 570/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 588 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 65/279 37/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 4258111 m, 58188 m/sec, 21476752 t fired, .
[[35mlola[0m][.] 62 EF STEQ 575/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 593 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 70/279 39/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 4572477 m, 62873 m/sec, 23066107 t fired, .
[[35mlola[0m][.] 62 EF STEQ 580/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 598 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 75/279 42/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 4890937 m, 63692 m/sec, 24735916 t fired, .
[[35mlola[0m][.] 62 EF STEQ 585/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 603 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 80/279 44/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 5213670 m, 64546 m/sec, 26397776 t fired, .
[[35mlola[0m][.] 62 EF STEQ 590/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 608 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 85/279 47/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 5505120 m, 58290 m/sec, 27908561 t fired, .
[[35mlola[0m][.] 62 EF STEQ 595/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 613 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 90/279 49/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 5819026 m, 62781 m/sec, 29520930 t fired, .
[[35mlola[0m][.] 62 EF STEQ 600/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 618 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 95/279 52/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 6130061 m, 62207 m/sec, 31175452 t fired, .
[[35mlola[0m][.] 62 EF STEQ 605/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 623 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 100/279 55/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 6448248 m, 63637 m/sec, 32821652 t fired, .
[[35mlola[0m][.] 62 EF STEQ 610/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 628 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 105/279 57/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 6763072 m, 62964 m/sec, 34471642 t fired, .
[[35mlola[0m][.] 62 EF STEQ 615/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 633 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 110/279 60/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 7077977 m, 62981 m/sec, 36125186 t fired, .
[[35mlola[0m][.] 62 EF STEQ 620/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 638 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 115/279 62/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 7386859 m, 61776 m/sec, 37783978 t fired, .
[[35mlola[0m][.] 62 EF STEQ 625/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 643 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 120/279 65/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 7701072 m, 62842 m/sec, 39435970 t fired, .
[[35mlola[0m][.] 62 EF STEQ 630/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 648 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 125/279 67/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 8017651 m, 63315 m/sec, 41095476 t fired, .
[[35mlola[0m][.] 62 EF STEQ 635/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 653 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 130/279 70/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 8328447 m, 62159 m/sec, 42767097 t fired, .
[[35mlola[0m][.] 62 EF STEQ 640/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 658 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 135/279 72/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 8638050 m, 61920 m/sec, 44430623 t fired, .
[[35mlola[0m][.] 62 EF STEQ 645/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 663 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 140/279 75/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 8950499 m, 62489 m/sec, 46087443 t fired, .
[[35mlola[0m][.] 62 EF STEQ 650/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 668 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 145/279 77/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 9259912 m, 61882 m/sec, 47752000 t fired, .
[[35mlola[0m][.] 62 EF STEQ 655/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 673 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 150/279 80/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 9570935 m, 62204 m/sec, 49403691 t fired, .
[[35mlola[0m][.] 62 EF STEQ 660/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 678 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 155/279 82/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 9880791 m, 61971 m/sec, 51055494 t fired, .
[[35mlola[0m][.] 62 EF STEQ 665/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 683 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 160/279 85/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 10191561 m, 62154 m/sec, 52703956 t fired, .
[[35mlola[0m][.] 62 EF STEQ 670/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 688 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 165/279 87/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 10453691 m, 52426 m/sec, 54159164 t fired, .
[[35mlola[0m][.] 62 EF STEQ 675/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 693 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 170/279 89/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 10715634 m, 52388 m/sec, 55588300 t fired, .
[[35mlola[0m][.] 62 EF STEQ 680/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 698 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 175/279 91/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 10984344 m, 53742 m/sec, 57005828 t fired, .
[[35mlola[0m][.] 62 EF STEQ 685/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 703 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 180/279 93/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 11263911 m, 55913 m/sec, 58521696 t fired, .
[[35mlola[0m][.] 62 EF STEQ 690/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 708 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 185/279 96/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 11566782 m, 60574 m/sec, 60170143 t fired, .
[[35mlola[0m][.] 62 EF STEQ 695/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 713 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 190/279 98/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 11873468 m, 61337 m/sec, 61815891 t fired, .
[[35mlola[0m][.] 62 EF STEQ 700/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 718 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 195/279 101/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 12179385 m, 61183 m/sec, 63460759 t fired, .
[[35mlola[0m][.] 62 EF STEQ 705/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 723 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 200/279 103/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 12484611 m, 61045 m/sec, 65106242 t fired, .
[[35mlola[0m][.] 62 EF STEQ 710/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 728 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 205/279 106/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 12789428 m, 60963 m/sec, 66747289 t fired, .
[[35mlola[0m][.] 62 EF STEQ 715/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 733 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 210/279 108/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 13088882 m, 59890 m/sec, 68398668 t fired, .
[[35mlola[0m][.] 62 EF STEQ 720/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 738 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 215/279 111/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 13389942 m, 60212 m/sec, 70041917 t fired, .
[[35mlola[0m][.] 62 EF STEQ 725/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 743 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 220/279 113/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 13692484 m, 60508 m/sec, 71680220 t fired, .
[[35mlola[0m][.] 62 EF STEQ 730/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 748 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 225/279 115/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 13998101 m, 61123 m/sec, 73316798 t fired, .
[[35mlola[0m][.] 62 EF STEQ 735/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 753 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 230/279 118/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 14298675 m, 60114 m/sec, 74957596 t fired, .
[[35mlola[0m][.] 62 EF STEQ 740/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 758 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 235/279 120/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 14599069 m, 60078 m/sec, 76601559 t fired, .
[[35mlola[0m][.] 62 EF STEQ 745/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 763 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 240/279 123/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 14896480 m, 59482 m/sec, 78249113 t fired, .
[[35mlola[0m][.] 62 EF STEQ 750/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 768 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 245/279 125/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 15193120 m, 59328 m/sec, 79902261 t fired, .
[[35mlola[0m][.] 62 EF STEQ 755/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 773 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 250/279 127/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 15493811 m, 60138 m/sec, 81545731 t fired, .
[[35mlola[0m][.] 62 EF STEQ 760/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 778 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 255/279 130/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 15792338 m, 59705 m/sec, 83197147 t fired, .
[[35mlola[0m][.] 62 EF STEQ 765/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 783 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 260/279 132/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 16092799 m, 60092 m/sec, 84843075 t fired, .
[[35mlola[0m][.] 62 EF STEQ 770/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 788 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 265/279 135/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 16394565 m, 60353 m/sec, 86486937 t fired, .
[[35mlola[0m][.] 62 EF STEQ 775/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 793 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 270/279 137/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 16694258 m, 59938 m/sec, 88127568 t fired, .
[[35mlola[0m][.] 62 EF STEQ 780/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 798 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 275/279 139/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 16974374 m, 56023 m/sec, 89656016 t fired, .
[[35mlola[0m][.] 62 EF STEQ 785/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 803 secs. Pages in use: 282
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 37 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EF STEQ 790/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 808 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 PolyORBLF-PT-S06J06T04-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 279 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 2792 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 198
[[35mlola[0m][I] fired transitions : 597
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 5/279 3/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 275422 m, -3339790 m/sec, 1534344 t fired, .
[[35mlola[0m][.] 62 EF STEQ 795/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 813 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 37 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 EF STEQ 800/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 818 secs. Pages in use: 289
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 PolyORBLF-PT-S06J06T04-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 309 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for PolyORBLF-PT-S06J06T04-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 394
[[35mlola[0m][I] fired transitions : 602
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 347 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 5/347 9/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 910270 m, 182054 m/sec, 1328996 t fired, .
[[35mlola[0m][.] 62 EF STEQ 805/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 823 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 10/347 17/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 1901154 m, 198176 m/sec, 2578962 t fired, .
[[35mlola[0m][.] 62 EF STEQ 810/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 828 secs. Pages in use: 301
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 15/347 26/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 2896331 m, 199035 m/sec, 3803825 t fired, .
[[35mlola[0m][.] 62 EF STEQ 815/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 833 secs. Pages in use: 310
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 20/347 34/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 3848427 m, 190419 m/sec, 4986766 t fired, .
[[35mlola[0m][.] 62 EF STEQ 820/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 838 secs. Pages in use: 318
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 25/347 41/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 4754894 m, 181293 m/sec, 6105044 t fired, .
[[35mlola[0m][.] 62 EF STEQ 825/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 843 secs. Pages in use: 325
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 30/347 49/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 5687333 m, 186487 m/sec, 7259304 t fired, .
[[35mlola[0m][.] 62 EF STEQ 830/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 848 secs. Pages in use: 333
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 35/347 56/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 6595035 m, 181540 m/sec, 8374390 t fired, .
[[35mlola[0m][.] 62 EF STEQ 835/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 853 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 40/347 64/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 7501336 m, 181260 m/sec, 9499778 t fired, .
[[35mlola[0m][.] 62 EF STEQ 840/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 858 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 45/347 71/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 8406025 m, 180937 m/sec, 10618318 t fired, .
[[35mlola[0m][.] 62 EF STEQ 845/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 863 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 50/347 79/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 9359809 m, 190756 m/sec, 11807271 t fired, .
[[35mlola[0m][.] 62 EF STEQ 850/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 868 secs. Pages in use: 363
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 55/347 87/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 10315432 m, 191124 m/sec, 12987168 t fired, .
[[35mlola[0m][.] 62 EF STEQ 855/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 873 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 60/347 94/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 11265065 m, 189926 m/sec, 14166835 t fired, .
[[35mlola[0m][.] 62 EF STEQ 860/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 878 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 65/347 102/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 12207665 m, 188520 m/sec, 15336577 t fired, .
[[35mlola[0m][.] 62 EF STEQ 865/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 883 secs. Pages in use: 386
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 70/347 109/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 13143832 m, 187233 m/sec, 16498100 t fired, .
[[35mlola[0m][.] 62 EF STEQ 870/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 888 secs. Pages in use: 393
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 75/347 117/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 14079136 m, 187060 m/sec, 17661284 t fired, .
[[35mlola[0m][.] 62 EF STEQ 875/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 893 secs. Pages in use: 401
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 80/347 124/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 15019729 m, 188118 m/sec, 18825782 t fired, .
[[35mlola[0m][.] 62 EF STEQ 880/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 898 secs. Pages in use: 408
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 85/347 132/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 15945226 m, 185099 m/sec, 19991847 t fired, .
[[35mlola[0m][.] 62 EF STEQ 885/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 903 secs. Pages in use: 416
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 90/347 139/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 16883316 m, 187618 m/sec, 21153394 t fired, .
[[35mlola[0m][.] 62 EF STEQ 890/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 908 secs. Pages in use: 423
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 95/347 145/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 17672678 m, 157872 m/sec, 22137759 t fired, .
[[35mlola[0m][.] 62 EF STEQ 895/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 913 secs. Pages in use: 429
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 100/347 152/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 18447174 m, 154899 m/sec, 23108548 t fired, .
[[35mlola[0m][.] 62 EF STEQ 900/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 918 secs. Pages in use: 436
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 105/347 158/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 19259929 m, 162551 m/sec, 24127517 t fired, .
[[35mlola[0m][.] 62 EF STEQ 905/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 923 secs. Pages in use: 442
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 110/347 164/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 20065384 m, 161091 m/sec, 25137233 t fired, .
[[35mlola[0m][.] 62 EF STEQ 910/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 928 secs. Pages in use: 448
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 115/347 171/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 20874847 m, 161892 m/sec, 26147049 t fired, .
[[35mlola[0m][.] 62 EF STEQ 915/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 933 secs. Pages in use: 455
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 120/347 177/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 21678842 m, 160799 m/sec, 27154716 t fired, .
[[35mlola[0m][.] 62 EF STEQ 920/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 938 secs. Pages in use: 461
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 125/347 184/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 22486819 m, 161595 m/sec, 28161817 t fired, .
[[35mlola[0m][.] 62 EF STEQ 925/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 943 secs. Pages in use: 468
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 130/347 190/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 23288442 m, 160324 m/sec, 29164767 t fired, .
[[35mlola[0m][.] 62 EF STEQ 930/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 948 secs. Pages in use: 474
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 135/347 196/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 24082063 m, 158724 m/sec, 30152034 t fired, .
[[35mlola[0m][.] 62 EF STEQ 935/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 953 secs. Pages in use: 480
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 140/347 202/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 24879380 m, 159463 m/sec, 31147918 t fired, .
[[35mlola[0m][.] 62 EF STEQ 940/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 958 secs. Pages in use: 486
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 145/347 209/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 25678572 m, 159838 m/sec, 32149045 t fired, .
[[35mlola[0m][.] 62 EF STEQ 945/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 963 secs. Pages in use: 493
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 150/347 215/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 26484007 m, 161087 m/sec, 33147918 t fired, .
[[35mlola[0m][.] 62 EF STEQ 950/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 968 secs. Pages in use: 499
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 155/347 221/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 27286931 m, 160584 m/sec, 34150232 t fired, .
[[35mlola[0m][.] 62 EF STEQ 955/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 973 secs. Pages in use: 505
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 160/347 228/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 28083478 m, 159309 m/sec, 35155451 t fired, .
[[35mlola[0m][.] 62 EF STEQ 960/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 978 secs. Pages in use: 512
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 165/347 234/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 28873241 m, 157952 m/sec, 36141592 t fired, .
[[35mlola[0m][.] 62 EF STEQ 965/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 983 secs. Pages in use: 518
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 170/347 240/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 29655358 m, 156423 m/sec, 37117259 t fired, .
[[35mlola[0m][.] 62 EF STEQ 970/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 988 secs. Pages in use: 524
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 175/347 246/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 30424591 m, 153846 m/sec, 38070101 t fired, .
[[35mlola[0m][.] 62 EF STEQ 975/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 993 secs. Pages in use: 530
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 180/347 252/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 31182570 m, 151595 m/sec, 39012575 t fired, .
[[35mlola[0m][.] 62 EF STEQ 980/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 998 secs. Pages in use: 536
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 185/347 258/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 31979902 m, 159466 m/sec, 40010454 t fired, .
[[35mlola[0m][.] 62 EF STEQ 985/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1003 secs. Pages in use: 542
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 190/347 265/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 32817936 m, 167606 m/sec, 41054758 t fired, .
[[35mlola[0m][.] 62 EF STEQ 990/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1008 secs. Pages in use: 549
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 195/347 271/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 33627330 m, 161878 m/sec, 42071621 t fired, .
[[35mlola[0m][.] 62 EF STEQ 995/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1013 secs. Pages in use: 555
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 200/347 272/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 33797984 m, 34130 m/sec, 42282848 t fired, .
[[35mlola[0m][.] 62 EF STEQ 1000/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1018 secs. Pages in use: 556
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-10: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S06J06T04-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S06J06T04-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-05: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-13: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S06J06T04-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 217/347 273/2000 PolyORBLF-PT-S06J06T04-CTLFireability-2024-08 33883966 m, 17196 m/sec, 42395594 t fired, .
[[35mlola[0m][.] 62 EF STEQ 1017/3582 0/5 PolyORBLF-PT-S06J06T04-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 557
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 412 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PolyORBLF-PT-S06J06T04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PolyORBLF-PT-S06J06T04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r291-tajo-171654448100338"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PolyORBLF-PT-S06J06T04.tgz
mv PolyORBLF-PT-S06J06T04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;