About the Execution of LoLA for PolyORBLF-PT-S04J04T08
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 0.000 | 987902.00 | 0.00 | 0.00 | ?F???T??T?F???F? | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r291-tajo-171654448000274.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PolyORBLF-PT-S04J04T08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r291-tajo-171654448000274
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.4M
-rw-r--r-- 1 mcc users 21K Apr 11 16:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 131K Apr 11 16:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 109K Apr 11 16:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 501K Apr 11 16:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 9.0K Apr 23 07:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 38K Apr 23 07:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 23 07:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 49K Apr 23 07:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 29K Apr 11 17:02 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 159K Apr 11 17:02 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 178K Apr 11 17:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 780K Apr 11 17:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.3K Apr 23 07:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.8K Apr 23 07:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 3.3M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-00
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-01
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-02
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-03
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-04
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-05
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-06
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-07
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-08
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-09
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-10
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-11
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-12
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-13
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-14
FORMULA_NAME PolyORBLF-PT-S04J04T08-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717061035526
FORMULA PolyORBLF-PT-S04J04T08-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S04J04T08-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S04J04T08-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S04J04T08-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S04J04T08-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717062023428
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 PolyORBLF-PT-S04J04T08-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-01: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-05: EXEF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-10: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-11: SP ECTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-14: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 CTL EXCL 2/199 1/2000 PolyORBLF-PT-S04J04T08-CTLFireability-2024-08 249 m, 49 m/sec, 499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 7 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for PolyORBLF-PT-S04J04T08-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 249
[[35mlola[0m][I] fired transitions : 499
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 PolyORBLF-PT-S04J04T08-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 23 PolyORBLF-PT-S04J04T08-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for PolyORBLF-PT-S04J04T08-CTLFireability-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1286
[[35mlola[0m][I] fired transitions : 1289
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 56 (type EXCL) for 23 PolyORBLF-PT-S04J04T08-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 63 (type FNDP) for 38 PolyORBLF-PT-S04J04T08-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 38 PolyORBLF-PT-S04J04T08-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type EXCL) for PolyORBLF-PT-S04J04T08-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 63
[[35mlola[0m][I] fired transitions : 62
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 61 (type EQUN) for PolyORBLF-PT-S04J04T08-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 PolyORBLF-PT-S04J04T08-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 3 PolyORBLF-PT-S04J04T08-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for PolyORBLF-PT-S04J04T08-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][W] CANCELED task # 63 (type FNDP) for PolyORBLF-PT-S04J04T08-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][I] FINISHED task # 63 (type FNDP) for PolyORBLF-PT-S04J04T08-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 2
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T08-CTLFireability-2024-05: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T08-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T08-CTLFireability-2024-10: EF false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T08-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-01: CONJ 0 3 1 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-11: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 5/256 7/2000 PolyORBLF-PT-S04J04T08-CTLFireability-2024-15 591295 m, 118259 m/sec, 616192 t fired, .
[[35mlola[0m][.] 68 EF STEQ 5/3593 0/5 PolyORBLF-PT-S04J04T08-CTLFireability-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 12 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T08-CTLFireability-2024-05: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T08-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T08-CTLFireability-2024-10: EF false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T08-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-01: CONJ 0 3 1 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-11: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 10/256 11/2000 PolyORBLF-PT-S04J04T08-CTLFireability-2024-15 968545 m, 75450 m/sec, 1011687 t fired, .
[[35mlola[0m][.] 68 EF STEQ 10/3593 0/5 PolyORBLF-PT-S04J04T08-CTLFireability-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T08-CTLFireability-2024-05: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T08-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T08-CTLFireability-2024-10: EF false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T08-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-01: CONJ 0 3 1 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-11: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 15/256 16/2000 PolyORBLF-PT-S04J04T08-CTLFireability-2024-15 1372642 m, 80819 m/sec, 1439586 t fired, .
[[35mlola[0m][.] 68 EF STEQ 15/3593 0/5 PolyORBLF-PT-S04J04T08-CTLFireability-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T08-CTLFireability-2024-05: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T08-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T08-CTLFireability-2024-10: EF false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T08-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-01: CONJ 0 3 1 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T08-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 54 CTL EXCL 35/326 43/2000 PolyORBLF-PT-S04J04T08-CTLFireability-2024-15 3949645 m, 153676 m/sec, 4201135 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 411 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PolyORBLF-PT-S04J04T08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PolyORBLF-PT-S04J04T08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r291-tajo-171654448000274"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PolyORBLF-PT-S04J04T08.tgz
mv PolyORBLF-PT-S04J04T08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;