About the Execution of LoLA for PolyORBLF-PT-S04J04T06
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
0.000 | 1533267.00 | 0.00 | 0.00 | ??????????T??FFF | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r291-tajo-171654447900266.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PolyORBLF-PT-S04J04T06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r291-tajo-171654447900266
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.3M
-rw-r--r-- 1 mcc users 17K Apr 11 17:03 CTLCardinality.txt
-rw-r--r-- 1 mcc users 103K Apr 11 17:03 CTLCardinality.xml
-rw-r--r-- 1 mcc users 29K Apr 11 17:01 CTLFireability.txt
-rw-r--r-- 1 mcc users 157K Apr 11 17:01 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 8.4K Apr 23 07:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 38K Apr 23 07:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Apr 23 07:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 33K Apr 23 07:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 21K Apr 11 17:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Apr 11 17:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 40K Apr 11 17:13 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 207K Apr 11 17:13 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.6K Apr 23 07:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.6K Apr 23 07:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 2.5M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-00
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-01
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-02
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-03
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-04
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-05
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-06
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-07
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-08
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-09
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-10
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-11
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-12
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-13
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-14
FORMULA_NAME PolyORBLF-PT-S04J04T06-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717060459628
FORMULA PolyORBLF-PT-S04J04T06-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S04J04T06-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S04J04T06-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-PT-S04J04T06-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717061992895
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 54 (type CNST) for 53 PolyORBLF-PT-S04J04T06-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 54 (type CNST) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 PolyORBLF-PT-S04J04T06-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type FNDP) for 38 PolyORBLF-PT-S04J04T06-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 38 PolyORBLF-PT-S04J04T06-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1538
[[35mlola[0m][I] fired transitions : 2892
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 56 (type FNDP) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 57 (type EQUN) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 50 PolyORBLF-PT-S04J04T06-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 2/256 4/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 380436 m, 76087 m/sec, 411466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 7/256 13/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 1455872 m, 215087 m/sec, 1597784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 12/256 21/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 2489402 m, 206706 m/sec, 2754641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 17/256 30/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 3485905 m, 199300 m/sec, 3878338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 22/256 38/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 4470185 m, 196856 m/sec, 5000147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 27/256 46/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 5437595 m, 193482 m/sec, 6114704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 32/256 54/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 6392718 m, 191024 m/sec, 7217741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 37/256 61/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 7338056 m, 189067 m/sec, 8316626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 42/256 69/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 8266450 m, 185678 m/sec, 9404990 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 47/256 76/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 9137382 m, 174186 m/sec, 10430922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 52/256 84/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 10077019 m, 187927 m/sec, 11538110 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 57/256 91/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 11011557 m, 186907 m/sec, 12648259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 62/256 99/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 11937003 m, 185089 m/sec, 13746688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 67/256 106/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 12863868 m, 185373 m/sec, 14855918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 72/256 114/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 13782266 m, 183679 m/sec, 15954983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 77/256 121/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 14698852 m, 183317 m/sec, 17054224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 82/256 129/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 15618470 m, 183923 m/sec, 18158853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 87/256 136/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 16549300 m, 186166 m/sec, 19277730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 92/256 144/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 17464408 m, 183021 m/sec, 20377535 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 97/256 151/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 18387683 m, 184655 m/sec, 21489496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 102/256 159/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 19300309 m, 182525 m/sec, 22593203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 107/256 166/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 20223145 m, 184567 m/sec, 23714192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 112/256 174/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 21140467 m, 183464 m/sec, 24829631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 117/256 181/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 22044900 m, 180886 m/sec, 25938819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 122/256 188/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 22950780 m, 181176 m/sec, 27035910 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 127/256 196/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 23859990 m, 181842 m/sec, 28138726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 132/256 204/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 24783477 m, 184697 m/sec, 29264252 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 137/256 211/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 25688460 m, 180996 m/sec, 30375975 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 142/256 218/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 26596458 m, 181599 m/sec, 31468091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 147/256 226/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 27502601 m, 181228 m/sec, 32597982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 152/256 234/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 28421222 m, 183724 m/sec, 33712292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 157/256 241/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 29325322 m, 180820 m/sec, 34823841 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 162/256 249/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 30230785 m, 181092 m/sec, 35918325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 167/256 256/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 31128975 m, 179638 m/sec, 37046311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 172/256 263/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 32031406 m, 180486 m/sec, 38149416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 177/256 271/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 32930391 m, 179797 m/sec, 39251785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 182/256 278/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 33832051 m, 180332 m/sec, 40351577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 187/256 285/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 34734698 m, 180529 m/sec, 41462942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 192/256 293/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 35624363 m, 177933 m/sec, 42573412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 197/256 300/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 36521507 m, 179428 m/sec, 43657378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 202/256 307/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 37387681 m, 173234 m/sec, 44733461 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 207/256 314/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 38252383 m, 172940 m/sec, 45812420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 212/256 321/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 39120736 m, 173670 m/sec, 46902231 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 321
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 217/256 329/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 40022554 m, 180363 m/sec, 48028807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 329
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 222/256 336/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 40913303 m, 178149 m/sec, 49146627 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 227/256 343/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 41803225 m, 177984 m/sec, 50243381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 232/256 350/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 42693212 m, 177997 m/sec, 51343833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 350
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 237/256 358/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 43582345 m, 177826 m/sec, 52455508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 358
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 242/256 365/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 44475325 m, 178596 m/sec, 53559469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 365
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 247/256 372/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 45365060 m, 177947 m/sec, 54668177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 252/256 380/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 46258714 m, 178730 m/sec, 55770457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 45 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 PolyORBLF-PT-S04J04T06-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 PolyORBLF-PT-S04J04T06-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 3334 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 677
[[35mlola[0m][I] fired transitions : 1354
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 45 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 PolyORBLF-PT-S04J04T06-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 277 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 681
[[35mlola[0m][I] fired transitions : 2038
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 25 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 302 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 5/302 6/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 678729 m, 135745 m/sec, 1434501 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 10/302 12/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 1369006 m, 138055 m/sec, 2907110 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 15/302 18/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 2044951 m, 135189 m/sec, 4352566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 20/302 23/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 2661534 m, 123316 m/sec, 5677702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 25/302 28/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 3301459 m, 127985 m/sec, 7057594 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 30/302 33/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 3909888 m, 121685 m/sec, 8373462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 35/302 39/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 4551920 m, 128406 m/sec, 9765630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 40/302 43/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 5133576 m, 116331 m/sec, 11029030 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 45/302 48/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 5757585 m, 124801 m/sec, 12388634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 50/302 54/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 6375252 m, 123533 m/sec, 13736877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 55/302 59/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 7002802 m, 125510 m/sec, 15112156 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 60/302 64/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 7622315 m, 123902 m/sec, 16468881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 65/302 69/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 8244213 m, 124379 m/sec, 17833494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 70/302 74/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 8864585 m, 124074 m/sec, 19196935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 75/302 78/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 9431562 m, 113395 m/sec, 20446827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 80/302 83/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 10042490 m, 122185 m/sec, 21793011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 85/302 88/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 10634295 m, 118361 m/sec, 23097028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 90/302 93/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 11251517 m, 123444 m/sec, 24462350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 95/302 98/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 11864092 m, 122515 m/sec, 25823836 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 100/302 103/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 12478847 m, 122951 m/sec, 27188606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 105/302 108/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 13090067 m, 122244 m/sec, 28544237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 110/302 113/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 13701642 m, 122315 m/sec, 29901494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 115/302 118/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 14307729 m, 121217 m/sec, 31246660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 120/302 123/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 14914803 m, 121414 m/sec, 32595802 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 125/302 128/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 15521507 m, 121340 m/sec, 33946685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 130/302 133/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 16126766 m, 121051 m/sec, 35295599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 135/302 138/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 16737607 m, 122168 m/sec, 36656618 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 140/302 143/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 17346980 m, 121874 m/sec, 38008848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 145/302 147/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 17895833 m, 109770 m/sec, 39233345 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 150/302 152/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 18475286 m, 115890 m/sec, 40519079 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 155/302 157/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 19067477 m, 118438 m/sec, 41838438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 160/302 162/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 19671519 m, 120808 m/sec, 43195026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 165/302 167/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 20271759 m, 120048 m/sec, 44533924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 170/302 172/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 20874703 m, 120588 m/sec, 45890970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 175/302 176/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 21471289 m, 119317 m/sec, 47217357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 180/302 181/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 22074887 m, 120719 m/sec, 48560843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 185/302 186/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 22670026 m, 119027 m/sec, 49884381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 190/302 191/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 23267603 m, 119515 m/sec, 51211532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 195/302 196/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 23866084 m, 119696 m/sec, 52536609 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 200/302 201/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 24468411 m, 120465 m/sec, 53882157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 205/302 206/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 25069206 m, 120159 m/sec, 55215845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 210/302 211/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 25669953 m, 120149 m/sec, 56552832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 215/302 215/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 26264782 m, 118965 m/sec, 57881647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 220/302 220/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 26860250 m, 119093 m/sec, 59219487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 491 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 225/302 225/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 27460790 m, 120108 m/sec, 60567634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 496 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 230/302 230/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 28057035 m, 119249 m/sec, 61914745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 501 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 235/302 235/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 28649492 m, 118491 m/sec, 63231876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 506 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 240/302 240/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 29245129 m, 119127 m/sec, 64560462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 511 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 245/302 245/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 29834253 m, 117824 m/sec, 65905009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 516 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 250/302 250/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 30431811 m, 119511 m/sec, 67243744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 521 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 255/302 254/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 30981708 m, 109979 m/sec, 68481789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 526 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 260/302 259/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 31568988 m, 117456 m/sec, 69797168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 531 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 265/302 264/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 32144633 m, 115129 m/sec, 71081760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 536 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 270/302 268/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 32719467 m, 114966 m/sec, 72402396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 541 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 275/302 273/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 33267569 m, 109620 m/sec, 73651092 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 546 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 280/302 277/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 33833917 m, 113269 m/sec, 74930122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 551 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 285/302 282/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 34429226 m, 119061 m/sec, 76256624 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 556 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 290/302 287/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 34997150 m, 113584 m/sec, 77532198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 561 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 295/302 292/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 35576702 m, 115910 m/sec, 78830869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 566 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 300/302 296/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 36113499 m, 107359 m/sec, 80057585 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 571 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 30 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ 0 1 0 0 2 1 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 576 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 25 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 302 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 25 PolyORBLF-PT-S04J04T06-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 3024 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 176516
[[35mlola[0m][I] fired transitions : 604975
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][W] CANCELED task # 30 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 PolyORBLF-PT-S04J04T06-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 335 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1220
[[35mlola[0m][I] fired transitions : 2822
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 PolyORBLF-PT-S04J04T06-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 377 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1402
[[35mlola[0m][I] fired transitions : 4194
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 431 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 3/431 2/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 198234 m, 39646 m/sec, 768050 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 581 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 8/431 5/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 541843 m, 68721 m/sec, 2135663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 586 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 13/431 8/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 874494 m, 66530 m/sec, 3452878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 591 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 18/431 12/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 1224899 m, 70081 m/sec, 4846641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 596 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 23/431 15/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 1553244 m, 65669 m/sec, 6239562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 601 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 28/431 18/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 1904078 m, 70166 m/sec, 7640681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 606 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 33/431 21/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 2248954 m, 68975 m/sec, 9043276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 611 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 38/431 24/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 2573234 m, 64856 m/sec, 10367531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 616 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 43/431 27/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 2913670 m, 68087 m/sec, 11763725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 621 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 48/431 30/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 3256004 m, 68466 m/sec, 13166674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 626 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 53/431 33/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 3596741 m, 68147 m/sec, 14557341 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 58/431 37/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 3941877 m, 69027 m/sec, 15948839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 636 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 63/431 40/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 4260966 m, 63817 m/sec, 17334336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 641 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 68/431 42/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 4563929 m, 60592 m/sec, 18621682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 646 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 73/431 45/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 4892999 m, 65814 m/sec, 19973098 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 651 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 78/431 48/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 5209249 m, 63250 m/sec, 21278987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 656 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 83/431 51/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 5543753 m, 66900 m/sec, 22654696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 661 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 88/431 55/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 5886189 m, 68487 m/sec, 24065476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 666 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 93/431 58/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 6223092 m, 67380 m/sec, 25472904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 671 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 98/431 61/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 6564141 m, 68209 m/sec, 26868873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 676 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 103/431 64/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 6899336 m, 67039 m/sec, 28272299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 681 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 108/431 67/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 7230706 m, 66274 m/sec, 29675508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 686 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 113/431 70/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 7573309 m, 68520 m/sec, 31067822 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 691 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 118/431 73/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 7902510 m, 65840 m/sec, 32460995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 696 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 123/431 76/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 8246979 m, 68893 m/sec, 33859476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 701 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 128/431 79/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 8576273 m, 65858 m/sec, 35257726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 706 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 133/431 82/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 8897052 m, 64155 m/sec, 36653178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 711 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 138/431 85/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 9199796 m, 60548 m/sec, 38047074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 716 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 143/431 88/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 9548122 m, 69665 m/sec, 39464690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 721 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 148/431 92/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 9894430 m, 69261 m/sec, 40873920 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 726 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 153/431 95/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 10229682 m, 67050 m/sec, 42281215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 731 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 158/431 98/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 10564957 m, 67055 m/sec, 43685649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 736 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 163/431 101/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 10901730 m, 67354 m/sec, 45093350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 741 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 168/431 104/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 11246315 m, 68917 m/sec, 46508398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 746 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 173/431 107/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 11586869 m, 68110 m/sec, 47929889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 751 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 178/431 110/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 11915095 m, 65645 m/sec, 49347126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 756 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 183/431 114/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 12257760 m, 68533 m/sec, 50754428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 761 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 188/431 117/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 12582096 m, 64867 m/sec, 52100431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 766 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 193/431 120/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 12904641 m, 64509 m/sec, 53466622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 771 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 198/431 123/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 13244476 m, 67967 m/sec, 54872067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 776 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 203/431 126/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 13581395 m, 67383 m/sec, 56284474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 781 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 208/431 129/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 13907916 m, 65304 m/sec, 57695696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 786 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 213/431 132/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 14246586 m, 67734 m/sec, 59097017 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 791 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 218/431 135/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 14589763 m, 68635 m/sec, 60495531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 796 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 223/431 138/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 14919448 m, 65937 m/sec, 61893379 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 801 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 228/431 141/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 15252641 m, 66638 m/sec, 63302855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 806 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 233/431 145/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 15594470 m, 68365 m/sec, 64705206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 811 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 238/431 148/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 15929249 m, 66955 m/sec, 66107669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 816 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 243/431 151/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 16248629 m, 63876 m/sec, 67508076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 821 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 248/431 154/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 16563350 m, 62944 m/sec, 68908899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 826 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 253/431 156/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 16870478 m, 61425 m/sec, 70245227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 831 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 258/431 159/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 17156865 m, 57277 m/sec, 71589963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 836 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 263/431 162/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 17487457 m, 66118 m/sec, 72916190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 841 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 268/431 165/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 17833591 m, 69226 m/sec, 74326110 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 846 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 273/431 169/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 18182344 m, 69750 m/sec, 75727245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 851 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 278/431 172/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 18520140 m, 67559 m/sec, 77133178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 856 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 283/431 175/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 18861228 m, 68217 m/sec, 78529496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 861 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 288/431 178/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 19197245 m, 67203 m/sec, 79928379 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 866 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 293/431 181/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 19532993 m, 67149 m/sec, 81331536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 871 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 298/431 185/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 19884017 m, 70204 m/sec, 82740032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 876 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 303/431 188/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 20233728 m, 69942 m/sec, 84153714 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 881 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 308/431 191/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 20577386 m, 68731 m/sec, 85570100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 886 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 313/431 194/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 20917860 m, 68094 m/sec, 86984693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 891 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 318/431 198/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 21247004 m, 65828 m/sec, 88396464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 896 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 323/431 201/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 21596069 m, 69813 m/sec, 89796914 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 901 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 328/431 204/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 21932089 m, 67204 m/sec, 91199719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 906 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 333/431 207/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 22272052 m, 67992 m/sec, 92592460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 911 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 338/431 210/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 22605313 m, 66652 m/sec, 93988137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 916 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 343/431 213/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 22943436 m, 67624 m/sec, 95386278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 921 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 348/431 217/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 23293104 m, 69933 m/sec, 96792681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 926 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 353/431 220/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 23628668 m, 67112 m/sec, 98199065 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 931 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 358/431 223/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 23953108 m, 64888 m/sec, 99602873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 936 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 363/431 226/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 24293894 m, 68157 m/sec, 101001990 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 941 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 368/431 229/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 24635392 m, 68299 m/sec, 102396505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 946 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 373/431 233/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 24982847 m, 69491 m/sec, 103792593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 951 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 378/431 236/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 25319887 m, 67408 m/sec, 105187812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 956 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 383/431 239/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 25648404 m, 65703 m/sec, 106576556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 961 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 388/431 242/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 25988045 m, 67928 m/sec, 107980152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 966 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 393/431 245/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 26330548 m, 68500 m/sec, 109377874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 971 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 398/431 248/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 26677468 m, 69384 m/sec, 110776705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 976 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 403/431 252/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 27015175 m, 67541 m/sec, 112173342 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 981 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 408/431 255/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 27345106 m, 65986 m/sec, 113561230 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 986 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 413/431 258/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 27651775 m, 61333 m/sec, 114961168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 991 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 418/431 261/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 27968997 m, 63444 m/sec, 116318125 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 996 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 423/431 263/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 28279738 m, 62148 m/sec, 117624766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1001 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 428/431 266/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 28587508 m, 61554 m/sec, 118947784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1006 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 14 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1011 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 6 PolyORBLF-PT-S04J04T06-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 431 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 2589 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 677
[[35mlola[0m][I] fired transitions : 677
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 5/431 4/5 PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 353632 m, -5646775 m/sec, 1384002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1016 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 14 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-03 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1021 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 PolyORBLF-PT-S04J04T06-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 515 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 784
[[35mlola[0m][I] fired transitions : 819
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 644 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 5/644 7/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 647394 m, 129478 m/sec, 1616976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1026 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 10/644 11/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 1182605 m, 107042 m/sec, 3263363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1031 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 15/644 16/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 1710465 m, 105572 m/sec, 4894687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1036 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 20/644 21/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 2268518 m, 111610 m/sec, 6633341 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1041 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 25/644 26/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 2809278 m, 108152 m/sec, 8364731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1046 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 30/644 31/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 3380739 m, 114292 m/sec, 10121336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1051 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 35/644 36/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 3951590 m, 114170 m/sec, 11883518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1056 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 40/644 41/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 4491311 m, 107944 m/sec, 13629707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1061 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 45/644 46/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 5053518 m, 112441 m/sec, 15363698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1066 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 50/644 51/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 5609887 m, 111273 m/sec, 17097151 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1071 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 55/644 56/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 6156668 m, 109356 m/sec, 18825416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1076 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 60/644 61/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 6724069 m, 113480 m/sec, 20575012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1081 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 65/644 66/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 7273117 m, 109809 m/sec, 22307960 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1086 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 70/644 71/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 7815759 m, 108528 m/sec, 24048465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1091 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 75/644 76/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 8380817 m, 113011 m/sec, 25783865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1096 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 80/644 81/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 8929586 m, 109753 m/sec, 27512772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1101 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 85/644 86/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 9477471 m, 109577 m/sec, 29248824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1106 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 90/644 91/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 10035749 m, 111655 m/sec, 30972408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1111 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 95/644 96/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 10584089 m, 109668 m/sec, 32691305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1116 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 100/644 101/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 11097724 m, 102727 m/sec, 34400326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1121 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 105/644 105/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 11627141 m, 105883 m/sec, 36104604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1126 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 110/644 110/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 12151148 m, 104801 m/sec, 37804165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1131 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 115/644 116/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 12753450 m, 120460 m/sec, 39489027 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1136 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 120/644 122/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-00 13464378 m, 142185 m/sec, 41158274 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1141 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for PolyORBLF-PT-S04J04T06-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 13865074
[[35mlola[0m][I] fired transitions : 42097976
[[35mlola[0m][I] time used : 123
[[35mlola[0m][I] memory pages used : 126
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 818 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 2/818 4/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 469352 m, 93870 m/sec, 546218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1146 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 7/818 11/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 1594938 m, 225117 m/sec, 1905265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1151 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 12/818 19/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 2646634 m, 210339 m/sec, 3222915 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1156 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 17/818 25/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 3588127 m, 188298 m/sec, 4435385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1161 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 22/818 31/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 4488719 m, 180118 m/sec, 5617792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1166 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 27/818 37/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 5450762 m, 192408 m/sec, 6898907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1171 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 32/818 44/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 6411546 m, 192156 m/sec, 8197404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1176 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 37/818 49/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 7281333 m, 173957 m/sec, 9385116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1181 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 42/818 55/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 8184595 m, 180652 m/sec, 10631531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1186 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 47/818 61/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 9127476 m, 188576 m/sec, 11936409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1191 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 52/818 67/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 10066704 m, 187845 m/sec, 13238076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1196 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 57/818 73/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 11006864 m, 188032 m/sec, 14556486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1201 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 62/818 80/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 11941888 m, 187004 m/sec, 15883139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1206 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 67/818 86/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 12875485 m, 186719 m/sec, 17191629 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1211 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 72/818 92/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 13816344 m, 188171 m/sec, 18523232 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1216 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 77/818 98/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 14747812 m, 186293 m/sec, 19853584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1221 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 82/818 104/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 15691280 m, 188693 m/sec, 21173546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1226 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 87/818 110/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 16613014 m, 184346 m/sec, 22506086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1231 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 92/818 116/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 17534838 m, 184364 m/sec, 23824828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1236 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 97/818 122/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 18455918 m, 184216 m/sec, 25131505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1241 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 102/818 128/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 19373345 m, 183485 m/sec, 26453558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1246 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 107/818 134/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 20289646 m, 183260 m/sec, 27754977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1251 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 112/818 140/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 21209604 m, 183991 m/sec, 29123315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1256 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 117/818 146/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 22132935 m, 184666 m/sec, 30476589 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1261 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 122/818 152/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 23036427 m, 180698 m/sec, 31771760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1266 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 127/818 158/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 23949156 m, 182545 m/sec, 33103028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1271 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 132/818 164/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 24860444 m, 182257 m/sec, 34425383 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1276 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 137/818 170/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 25777126 m, 183336 m/sec, 35741146 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1281 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 142/818 176/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 26689825 m, 182539 m/sec, 37099368 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1286 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 147/818 182/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 27602825 m, 182600 m/sec, 38426898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1291 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 152/818 188/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 28495137 m, 178462 m/sec, 39804351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1296 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 157/818 194/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 29391781 m, 179328 m/sec, 41185734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1301 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 162/818 199/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 30227012 m, 167046 m/sec, 42504491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1306 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 167/818 205/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 31095906 m, 173778 m/sec, 43848134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1311 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 172/818 210/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 31936442 m, 168107 m/sec, 45141476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1316 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 177/818 216/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 32815598 m, 175831 m/sec, 46555269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1321 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 182/818 222/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 33691277 m, 175135 m/sec, 47981977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1326 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 187/818 228/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 34560424 m, 173829 m/sec, 49381786 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1331 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 192/818 233/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 35414063 m, 170727 m/sec, 50788114 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1336 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 197/818 239/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 36284973 m, 174182 m/sec, 52202039 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1341 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 202/818 245/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 37171739 m, 177353 m/sec, 53526850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1346 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 207/818 250/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 38044244 m, 174501 m/sec, 54904650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1351 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 212/818 256/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 38882491 m, 167649 m/sec, 56303446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1356 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 217/818 261/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 39724839 m, 168469 m/sec, 57685515 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1361 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 222/818 267/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 40588953 m, 172822 m/sec, 59046398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1366 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 227/818 272/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 41440353 m, 170280 m/sec, 60433937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1371 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 232/818 278/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 42284203 m, 168770 m/sec, 61885134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1376 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 237/818 283/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 43156187 m, 174396 m/sec, 63281979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1381 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 242/818 289/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 44017252 m, 172213 m/sec, 64718741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1386 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 247/818 294/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 44860368 m, 168623 m/sec, 66114733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1391 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 252/818 300/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 45740337 m, 175993 m/sec, 67526432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1396 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 257/818 305/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 46591876 m, 170307 m/sec, 68892443 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1401 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 262/818 311/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 47452531 m, 172131 m/sec, 70273601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1406 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 267/818 317/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 48316138 m, 172721 m/sec, 71611418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1411 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 272/818 322/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 49161184 m, 169009 m/sec, 73032825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1416 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 277/818 328/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 50006116 m, 168986 m/sec, 74496916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1421 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 282/818 333/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 50830200 m, 164816 m/sec, 75877510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1426 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 287/818 338/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 51668347 m, 167629 m/sec, 77270712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1431 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 292/818 343/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 52519851 m, 170300 m/sec, 78598033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1436 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 297/818 349/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 53364189 m, 168867 m/sec, 79953337 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1441 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 302/818 354/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 54215914 m, 170345 m/sec, 81317090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1446 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 307/818 360/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 55028719 m, 162561 m/sec, 82741178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1451 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 312/818 365/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 55852252 m, 164706 m/sec, 84030219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1456 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 317/818 370/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 56631229 m, 155795 m/sec, 85298033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1461 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 322/818 375/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 57468895 m, 167533 m/sec, 86623019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1466 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 327/818 381/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 58302839 m, 166788 m/sec, 87923649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1471 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 332/818 386/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 59133526 m, 166137 m/sec, 89202628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1476 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 337/818 392/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 59950678 m, 163430 m/sec, 90462123 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1481 secs. Pages in use: 392
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 342/818 397/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 60744681 m, 158800 m/sec, 91728360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1486 secs. Pages in use: 397
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 347/818 402/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 61550490 m, 161161 m/sec, 92920559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1491 secs. Pages in use: 402
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 352/818 408/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 62395027 m, 168907 m/sec, 94210991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1496 secs. Pages in use: 408
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 357/818 413/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 63242903 m, 169575 m/sec, 95493797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1501 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 362/818 419/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 64084284 m, 168276 m/sec, 96781405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1506 secs. Pages in use: 419
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 367/818 424/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 64925142 m, 168171 m/sec, 98105410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1511 secs. Pages in use: 424
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 372/818 429/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 65665615 m, 148094 m/sec, 99234384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1516 secs. Pages in use: 429
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 383/818 431/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 65969583 m, 60793 m/sec, 99697318 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1527 secs. Pages in use: 431
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-07: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-PT-S04J04T06-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-14: F false state equation[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-PT-S04J04T06-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-02: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-PT-S04J04T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 389/818 432/2000 PolyORBLF-PT-S04J04T06-CTLFireability-2024-09 66103778 m, 26839 m/sec, 99896344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1533 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PolyORBLF-PT-S04J04T06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PolyORBLF-PT-S04J04T06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r291-tajo-171654447900266"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PolyORBLF-PT-S04J04T06.tgz
mv PolyORBLF-PT-S04J04T06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;