About the Execution of LoLA for PolyORBLF-COL-S06J06T06
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
0.000 | 940096.00 | 0.00 | 0.00 | ?FT?????????TF?? | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r291-tajo-171654447800202.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PolyORBLF-COL-S06J06T06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r291-tajo-171654447800202
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 544K
-rw-r--r-- 1 mcc users 6.5K Apr 11 17:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Apr 11 17:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Apr 11 17:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K Apr 11 17:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 23 07:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 07:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 23 07:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.8K Apr 11 17:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 70K Apr 11 17:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 11 17:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 86K Apr 11 17:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 23 07:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 154K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-00
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-01
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-02
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-03
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-04
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-05
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-06
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-07
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-08
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-09
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-10
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-11
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-12
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-13
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-14
FORMULA_NAME PolyORBLF-COL-S06J06T06-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717056987916
FORMULA PolyORBLF-COL-S06J06T06-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-COL-S06J06T06-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-COL-S06J06T06-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-COL-S06J06T06-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717057928012
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/FNDP) for 3 PolyORBLF-COL-S06J06T06-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 59 (type SKEL/EQUN) for 3 PolyORBLF-COL-S06J06T06-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH) for 3 PolyORBLF-COL-S06J06T06-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/SRCH) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 77
[[35mlola[0m][I] fired transitions : 76
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 58 (type FNDP) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-01 (obsolete)
[[35mlola[0m][W] CANCELED task # 59 (type EQUN) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-01 (obsolete)
[[35mlola[0m][I] LAUNCH task # 62 (type SKEL/FNDP) for 6 PolyORBLF-COL-S06J06T06-CTLFireability-2024-02
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type SKEL/EQUN) for 6 PolyORBLF-COL-S06J06T06-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 64 (type SKEL/SRCH) for 6 PolyORBLF-COL-S06J06T06-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type SKEL/SRCH) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 23
[[35mlola[0m][I] fired transitions : 22
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 62 (type FNDP) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 63 (type EQUN) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 58 (type SKEL/FNDP) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 62 (type SKEL/FNDP) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] findlow criterion violated for transition 59
[[35mlola[0m][I] Places: 700, Transitions: 10740
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] FINISHED task # 63 (type SKEL/EQUN) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 59 (type SKEL/EQUN) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-01
[[35mlola[0m][I] result : unknown
[[35mlola[0m][W] findlow criterion violated for transition 38
[[35mlola[0m][W] findlow criterion violated for transition 60
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][W] findlow criterion violated for transition 4
[[35mlola[0m][W] findlow criterion violated for transition 23
[[35mlola[0m][W] findlow criterion violated for transition 9
[[35mlola[0m][W] findlow criterion violated for 16 clusters
[[35mlola[0m][I] Time for checking findlow: 3
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 7/199 1/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 2 m, 0 m/sec, 4 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 12/199 4/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 273146 m, 54628 m/sec, 1117559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 33 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 33 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type FNDP) for 3 PolyORBLF-COL-S06J06T06-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-11
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 75 (type FNDP) for 6 PolyORBLF-COL-S06J06T06-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 75 (type FNDP) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 3 PolyORBLF-COL-S06J06T06-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type FNDP) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 136
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 73 (type EQUN) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-01 (obsolete)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 17/224 7/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 531230 m, 51616 m/sec, 2174986 t fired, .
[[35mlola[0m][.] 70 EF STEQ 5/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 22/224 11/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 814439 m, 56641 m/sec, 3337393 t fired, .
[[35mlola[0m][.] 70 EF STEQ 10/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 27/224 14/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 1083065 m, 53725 m/sec, 4441425 t fired, .
[[35mlola[0m][.] 70 EF STEQ 15/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 32/224 18/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 1381774 m, 59741 m/sec, 5669727 t fired, .
[[35mlola[0m][.] 70 EF STEQ 20/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 37/224 21/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 1685379 m, 60721 m/sec, 6918800 t fired, .
[[35mlola[0m][.] 70 EF STEQ 25/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 42/224 25/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 2000697 m, 63063 m/sec, 8217580 t fired, .
[[35mlola[0m][.] 70 EF STEQ 30/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 47/224 29/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 2312907 m, 62442 m/sec, 9505321 t fired, .
[[35mlola[0m][.] 70 EF STEQ 35/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 52/224 33/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 2621633 m, 61745 m/sec, 10778546 t fired, .
[[35mlola[0m][.] 70 EF STEQ 40/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 57/224 36/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 2909462 m, 57565 m/sec, 11967633 t fired, .
[[35mlola[0m][.] 70 EF STEQ 45/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 62/224 40/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 3209042 m, 59916 m/sec, 13206219 t fired, .
[[35mlola[0m][.] 70 EF STEQ 50/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 67/224 43/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 3486623 m, 55516 m/sec, 14355788 t fired, .
[[35mlola[0m][.] 70 EF STEQ 55/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 72/224 46/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 3779278 m, 58531 m/sec, 15567127 t fired, .
[[35mlola[0m][.] 70 EF STEQ 60/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 77/224 50/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 4084303 m, 61005 m/sec, 16831679 t fired, .
[[35mlola[0m][.] 70 EF STEQ 65/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 82/224 54/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 4392965 m, 61732 m/sec, 18114364 t fired, .
[[35mlola[0m][.] 70 EF STEQ 70/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 87/224 57/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 4696382 m, 60683 m/sec, 19391525 t fired, .
[[35mlola[0m][.] 70 EF STEQ 75/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 92/224 61/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 4987465 m, 58216 m/sec, 20601194 t fired, .
[[35mlola[0m][.] 70 EF STEQ 80/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 97/224 64/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 5276196 m, 57746 m/sec, 21824472 t fired, .
[[35mlola[0m][.] 70 EF STEQ 85/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 102/224 68/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 5571472 m, 59055 m/sec, 23060232 t fired, .
[[35mlola[0m][.] 70 EF STEQ 90/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 107/224 71/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 5876208 m, 60947 m/sec, 24332245 t fired, .
[[35mlola[0m][.] 70 EF STEQ 95/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 112/224 75/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 6182286 m, 61215 m/sec, 25631920 t fired, .
[[35mlola[0m][.] 70 EF STEQ 100/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 117/224 79/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 6489949 m, 61532 m/sec, 26919481 t fired, .
[[35mlola[0m][.] 70 EF STEQ 105/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 122/224 82/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 6798929 m, 61796 m/sec, 28210058 t fired, .
[[35mlola[0m][.] 70 EF STEQ 110/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 127/224 86/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 7102848 m, 60783 m/sec, 29491271 t fired, .
[[35mlola[0m][.] 70 EF STEQ 115/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 132/224 89/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 7383103 m, 56051 m/sec, 30662768 t fired, .
[[35mlola[0m][.] 70 EF STEQ 120/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 137/224 92/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 7659011 m, 55181 m/sec, 31900665 t fired, .
[[35mlola[0m][.] 70 EF STEQ 125/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 142/224 96/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 7952210 m, 58639 m/sec, 33129673 t fired, .
[[35mlola[0m][.] 70 EF STEQ 130/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 147/224 99/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 8228655 m, 55289 m/sec, 34287370 t fired, .
[[35mlola[0m][.] 70 EF STEQ 135/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 152/224 103/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 8519518 m, 58172 m/sec, 35529580 t fired, .
[[35mlola[0m][.] 70 EF STEQ 140/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 157/224 106/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 8822155 m, 60527 m/sec, 36837970 t fired, .
[[35mlola[0m][.] 70 EF STEQ 145/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 162/224 110/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 9125258 m, 60620 m/sec, 38113357 t fired, .
[[35mlola[0m][.] 70 EF STEQ 150/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 167/224 113/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 9426349 m, 60218 m/sec, 39401548 t fired, .
[[35mlola[0m][.] 70 EF STEQ 155/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 172/224 117/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 9729713 m, 60672 m/sec, 40683352 t fired, .
[[35mlola[0m][.] 70 EF STEQ 160/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 177/224 120/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 10008435 m, 55744 m/sec, 41914555 t fired, .
[[35mlola[0m][.] 70 EF STEQ 165/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 182/224 123/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 10302736 m, 58860 m/sec, 43154744 t fired, .
[[35mlola[0m][.] 70 EF STEQ 170/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 187/224 126/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 10573384 m, 54129 m/sec, 44333740 t fired, .
[[35mlola[0m][.] 70 EF STEQ 175/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 192/224 130/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 10876210 m, 60565 m/sec, 45614780 t fired, .
[[35mlola[0m][.] 70 EF STEQ 180/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 197/224 133/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 11158842 m, 56526 m/sec, 46816501 t fired, .
[[35mlola[0m][.] 70 EF STEQ 185/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 202/224 136/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 11433586 m, 54948 m/sec, 48079169 t fired, .
[[35mlola[0m][.] 70 EF STEQ 190/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 207/224 139/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 11699084 m, 53099 m/sec, 49279846 t fired, .
[[35mlola[0m][.] 70 EF STEQ 195/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 212/224 143/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 11995503 m, 59283 m/sec, 50536566 t fired, .
[[35mlola[0m][.] 70 EF STEQ 200/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 217/224 146/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 12271201 m, 55139 m/sec, 51771011 t fired, .
[[35mlola[0m][.] 70 EF STEQ 205/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 222/224 149/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 12570691 m, 59898 m/sec, 53074912 t fired, .
[[35mlola[0m][.] 70 EF STEQ 210/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 25 (type EXCL) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 70 EF STEQ 215/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 3365 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 5/3365 4/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 309010 m, -2452336 m/sec, 1264413 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 5/224 4/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 353128 m, 70625 m/sec, 1007550 t fired, .
[[35mlola[0m][.] 70 EF STEQ 220/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 25 (type EXCL) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-08 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 10/210 8/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 692298 m, 67834 m/sec, 1977035 t fired, .
[[35mlola[0m][.] 70 EF STEQ 225/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 15/224 12/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 1073124 m, 76165 m/sec, 3059188 t fired, .
[[35mlola[0m][.] 70 EF STEQ 230/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 20/224 17/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 1451921 m, 75759 m/sec, 4143483 t fired, .
[[35mlola[0m][.] 70 EF STEQ 235/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 25/224 21/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 1830243 m, 75664 m/sec, 5224183 t fired, .
[[35mlola[0m][.] 70 EF STEQ 240/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 30/224 25/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 2210328 m, 76017 m/sec, 6303621 t fired, .
[[35mlola[0m][.] 70 EF STEQ 245/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 35/224 29/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 2590807 m, 76095 m/sec, 7385119 t fired, .
[[35mlola[0m][.] 70 EF STEQ 250/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 40/224 33/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 2970242 m, 75887 m/sec, 8466241 t fired, .
[[35mlola[0m][.] 70 EF STEQ 255/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 45/224 37/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 3348317 m, 75615 m/sec, 9542672 t fired, .
[[35mlola[0m][.] 70 EF STEQ 260/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 50/224 41/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 3725487 m, 75434 m/sec, 10626884 t fired, .
[[35mlola[0m][.] 70 EF STEQ 265/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 55/224 46/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 4103179 m, 75538 m/sec, 11705153 t fired, .
[[35mlola[0m][.] 70 EF STEQ 270/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 60/224 50/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 4483448 m, 76053 m/sec, 12781494 t fired, .
[[35mlola[0m][.] 70 EF STEQ 275/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 65/224 54/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 4860986 m, 75507 m/sec, 13855479 t fired, .
[[35mlola[0m][.] 70 EF STEQ 280/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 70/224 58/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 5237672 m, 75337 m/sec, 14933170 t fired, .
[[35mlola[0m][.] 70 EF STEQ 285/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 75/224 62/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 5593568 m, 71179 m/sec, 15944458 t fired, .
[[35mlola[0m][.] 70 EF STEQ 290/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 80/224 66/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 5975361 m, 76358 m/sec, 17033590 t fired, .
[[35mlola[0m][.] 70 EF STEQ 295/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 85/224 70/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 6353482 m, 75624 m/sec, 18104920 t fired, .
[[35mlola[0m][.] 70 EF STEQ 300/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 90/224 74/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 6690601 m, 67423 m/sec, 19075393 t fired, .
[[35mlola[0m][.] 70 EF STEQ 305/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 95/224 77/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 7051929 m, 72265 m/sec, 20110016 t fired, .
[[35mlola[0m][.] 70 EF STEQ 310/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 100/224 81/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 7422520 m, 74118 m/sec, 21158878 t fired, .
[[35mlola[0m][.] 70 EF STEQ 315/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 105/224 85/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 7792497 m, 73995 m/sec, 22218780 t fired, .
[[35mlola[0m][.] 70 EF STEQ 320/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 110/224 89/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 8165597 m, 74620 m/sec, 23286580 t fired, .
[[35mlola[0m][.] 70 EF STEQ 325/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 115/224 93/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 8537630 m, 74406 m/sec, 24354525 t fired, .
[[35mlola[0m][.] 70 EF STEQ 330/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 120/224 97/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 8912355 m, 74945 m/sec, 25425203 t fired, .
[[35mlola[0m][.] 70 EF STEQ 335/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 125/224 101/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 9252093 m, 67947 m/sec, 26403959 t fired, .
[[35mlola[0m][.] 70 EF STEQ 340/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 130/224 105/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 9614189 m, 72419 m/sec, 27444286 t fired, .
[[35mlola[0m][.] 70 EF STEQ 345/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 135/224 109/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 9955206 m, 68203 m/sec, 28425176 t fired, .
[[35mlola[0m][.] 70 EF STEQ 350/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 140/224 112/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 10319715 m, 72901 m/sec, 29475534 t fired, .
[[35mlola[0m][.] 70 EF STEQ 355/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 145/224 116/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 10688407 m, 73738 m/sec, 30539859 t fired, .
[[35mlola[0m][.] 70 EF STEQ 360/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 150/224 120/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 11063324 m, 74983 m/sec, 31609089 t fired, .
[[35mlola[0m][.] 70 EF STEQ 365/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 155/224 124/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 11431075 m, 73550 m/sec, 32674906 t fired, .
[[35mlola[0m][.] 70 EF STEQ 370/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 160/224 128/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 11802201 m, 74225 m/sec, 33741138 t fired, .
[[35mlola[0m][.] 70 EF STEQ 375/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 281
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 165/224 132/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 12172361 m, 74032 m/sec, 34807898 t fired, .
[[35mlola[0m][.] 70 EF STEQ 380/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 170/224 136/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 12539833 m, 73494 m/sec, 35872059 t fired, .
[[35mlola[0m][.] 70 EF STEQ 385/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 289
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 175/224 140/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 12907344 m, 73502 m/sec, 36929256 t fired, .
[[35mlola[0m][.] 70 EF STEQ 390/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 180/224 144/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 13230623 m, 64655 m/sec, 37867057 t fired, .
[[35mlola[0m][.] 70 EF STEQ 395/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 297
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 185/224 147/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 13568211 m, 67517 m/sec, 38845584 t fired, .
[[35mlola[0m][.] 70 EF STEQ 400/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 190/224 151/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 13903224 m, 67002 m/sec, 39814270 t fired, .
[[35mlola[0m][.] 70 EF STEQ 405/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 304
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 195/224 154/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 14232986 m, 65952 m/sec, 40768215 t fired, .
[[35mlola[0m][.] 70 EF STEQ 410/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 200/224 158/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 14586044 m, 70611 m/sec, 41789716 t fired, .
[[35mlola[0m][.] 70 EF STEQ 415/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 311
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 205/224 162/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 14923284 m, 67448 m/sec, 42762107 t fired, .
[[35mlola[0m][.] 70 EF STEQ 420/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 210/224 166/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 15281409 m, 71625 m/sec, 43795891 t fired, .
[[35mlola[0m][.] 70 EF STEQ 425/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 319
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 215/224 169/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 15647187 m, 73155 m/sec, 44858711 t fired, .
[[35mlola[0m][.] 70 EF STEQ 430/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 220/224 173/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 16012574 m, 73077 m/sec, 45916362 t fired, .
[[35mlola[0m][.] 70 EF STEQ 435/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 54 (type EXCL) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 70 EF STEQ 440/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 330
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 PolyORBLF-COL-S06J06T06-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 3140 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 5/224 5/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 359183 m, -3130678 m/sec, 1024120 t fired, .
[[35mlola[0m][.] 70 EF STEQ 445/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 335
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 54 (type EXCL) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 70 EF STEQ 450/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 335
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 PolyORBLF-COL-S06J06T06-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 23
[[35mlola[0m][I] fired transitions : 27
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 33 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 260 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 284 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 5/284 7/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 540286 m, 108057 m/sec, 1091420 t fired, .
[[35mlola[0m][.] 70 EF STEQ 455/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 337
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 10/284 14/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 1093231 m, 110589 m/sec, 2210840 t fired, .
[[35mlola[0m][.] 70 EF STEQ 460/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 344
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 15/284 21/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 1639290 m, 109211 m/sec, 3318562 t fired, .
[[35mlola[0m][.] 70 EF STEQ 465/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 20/284 28/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 2179479 m, 108037 m/sec, 4415484 t fired, .
[[35mlola[0m][.] 70 EF STEQ 470/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 358
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 25/284 35/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 2724487 m, 109001 m/sec, 5524727 t fired, .
[[35mlola[0m][.] 70 EF STEQ 475/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 365
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 30/284 42/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 3272524 m, 109607 m/sec, 6641104 t fired, .
[[35mlola[0m][.] 70 EF STEQ 480/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 35/284 48/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 3771181 m, 99731 m/sec, 7659214 t fired, .
[[35mlola[0m][.] 70 EF STEQ 485/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 40/284 55/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 4296172 m, 104998 m/sec, 8732684 t fired, .
[[35mlola[0m][.] 70 EF STEQ 490/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 385
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 45/284 61/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 4785359 m, 97837 m/sec, 9733905 t fired, .
[[35mlola[0m][.] 70 EF STEQ 495/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 391
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 50/284 67/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 5302335 m, 103395 m/sec, 10793536 t fired, .
[[35mlola[0m][.] 70 EF STEQ 500/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 397
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 55/284 74/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 5801938 m, 99920 m/sec, 11831046 t fired, .
[[35mlola[0m][.] 70 EF STEQ 505/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 404
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 60/284 80/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 6298898 m, 99392 m/sec, 12852939 t fired, .
[[35mlola[0m][.] 70 EF STEQ 510/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 410
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 65/284 86/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 6800084 m, 100237 m/sec, 13902614 t fired, .
[[35mlola[0m][.] 70 EF STEQ 515/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 416
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 70/284 92/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 7319678 m, 103918 m/sec, 14973476 t fired, .
[[35mlola[0m][.] 70 EF STEQ 520/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 422
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 75/284 99/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 7820249 m, 100114 m/sec, 16022759 t fired, .
[[35mlola[0m][.] 70 EF STEQ 525/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 429
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 80/284 105/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 8324901 m, 100930 m/sec, 17065593 t fired, .
[[35mlola[0m][.] 70 EF STEQ 530/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 435
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 85/284 111/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 8821259 m, 99271 m/sec, 18100551 t fired, .
[[35mlola[0m][.] 70 EF STEQ 535/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 441
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 90/284 117/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 9322552 m, 100258 m/sec, 19138009 t fired, .
[[35mlola[0m][.] 70 EF STEQ 540/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 447
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 95/284 121/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 9700212 m, 75532 m/sec, 20298469 t fired, .
[[35mlola[0m][.] 70 EF STEQ 545/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 451
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 100/284 128/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 10198261 m, 99609 m/sec, 21334201 t fired, .
[[35mlola[0m][.] 70 EF STEQ 550/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 458
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 105/284 134/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 10693439 m, 99035 m/sec, 22383214 t fired, .
[[35mlola[0m][.] 70 EF STEQ 555/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 464
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 110/284 139/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 11139743 m, 89260 m/sec, 23481761 t fired, .
[[35mlola[0m][.] 70 EF STEQ 560/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 469
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 115/284 145/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 11603747 m, 92800 m/sec, 24584422 t fired, .
[[35mlola[0m][.] 70 EF STEQ 565/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 475
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 120/284 151/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 12110699 m, 101390 m/sec, 25653360 t fired, .
[[35mlola[0m][.] 70 EF STEQ 570/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 481
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 125/284 157/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 12604689 m, 98798 m/sec, 26717224 t fired, .
[[35mlola[0m][.] 70 EF STEQ 575/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 487
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 130/284 163/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 13088549 m, 96772 m/sec, 27771007 t fired, .
[[35mlola[0m][.] 70 EF STEQ 580/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 493
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 135/284 169/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 13573602 m, 97010 m/sec, 28815473 t fired, .
[[35mlola[0m][.] 70 EF STEQ 585/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 499
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 140/284 174/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 14052924 m, 95864 m/sec, 29877656 t fired, .
[[35mlola[0m][.] 70 EF STEQ 590/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 504
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 145/284 180/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 14519230 m, 93261 m/sec, 30944090 t fired, .
[[35mlola[0m][.] 70 EF STEQ 595/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 510
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 150/284 184/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 14906581 m, 77470 m/sec, 32070806 t fired, .
[[35mlola[0m][.] 70 EF STEQ 600/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 514
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 155/284 190/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 15375384 m, 93760 m/sec, 33124203 t fired, .
[[35mlola[0m][.] 70 EF STEQ 605/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 520
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 160/284 195/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 15837760 m, 92475 m/sec, 34166974 t fired, .
[[35mlola[0m][.] 70 EF STEQ 610/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 525
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 165/284 200/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 16265695 m, 85587 m/sec, 35237388 t fired, .
[[35mlola[0m][.] 70 EF STEQ 615/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 530
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 170/284 206/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 16743834 m, 95627 m/sec, 36253331 t fired, .
[[35mlola[0m][.] 70 EF STEQ 620/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 536
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 175/284 212/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 17228948 m, 97022 m/sec, 37275982 t fired, .
[[35mlola[0m][.] 70 EF STEQ 625/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 542
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 180/284 218/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 17682309 m, 90672 m/sec, 38331657 t fired, .
[[35mlola[0m][.] 70 EF STEQ 630/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 548
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 185/284 223/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 18142320 m, 92002 m/sec, 39394417 t fired, .
[[35mlola[0m][.] 70 EF STEQ 635/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 553
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 190/284 229/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 18625700 m, 96676 m/sec, 40432489 t fired, .
[[35mlola[0m][.] 70 EF STEQ 640/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 559
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 195/284 234/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 19041246 m, 83109 m/sec, 41492460 t fired, .
[[35mlola[0m][.] 70 EF STEQ 645/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 564
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 200/284 239/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 19475531 m, 86857 m/sec, 42517094 t fired, .
[[35mlola[0m][.] 70 EF STEQ 650/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 569
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 205/284 244/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 19890209 m, 82935 m/sec, 43531164 t fired, .
[[35mlola[0m][.] 70 EF STEQ 655/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 210/284 250/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 20372801 m, 96518 m/sec, 44568476 t fired, .
[[35mlola[0m][.] 70 EF STEQ 660/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 580
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 215/284 255/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 20844680 m, 94375 m/sec, 45571335 t fired, .
[[35mlola[0m][.] 70 EF STEQ 665/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 585
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 220/284 261/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 21317703 m, 94604 m/sec, 46609061 t fired, .
[[35mlola[0m][.] 70 EF STEQ 670/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 591
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 225/284 266/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 21719367 m, 80332 m/sec, 47639298 t fired, .
[[35mlola[0m][.] 70 EF STEQ 675/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 596
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 230/284 269/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 22037353 m, 63597 m/sec, 48765965 t fired, .
[[35mlola[0m][.] 70 EF STEQ 680/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 599
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 235/284 274/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 22487115 m, 89952 m/sec, 49761563 t fired, .
[[35mlola[0m][.] 70 EF STEQ 685/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 604
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 240/284 279/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 22910235 m, 84624 m/sec, 50860676 t fired, .
[[35mlola[0m][.] 70 EF STEQ 690/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 609
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 245/284 284/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 23342613 m, 86475 m/sec, 51881168 t fired, .
[[35mlola[0m][.] 70 EF STEQ 695/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 614
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 250/284 289/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 23711586 m, 73794 m/sec, 52944266 t fired, .
[[35mlola[0m][.] 70 EF STEQ 700/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 619
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 255/284 293/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 24067621 m, 71207 m/sec, 53999603 t fired, .
[[35mlola[0m][.] 70 EF STEQ 705/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 623
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 260/284 297/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 24467972 m, 80070 m/sec, 55088491 t fired, .
[[35mlola[0m][.] 70 EF STEQ 710/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 627
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 265/284 303/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 24922066 m, 90818 m/sec, 56071309 t fired, .
[[35mlola[0m][.] 70 EF STEQ 715/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 633
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 270/284 308/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 25358936 m, 87374 m/sec, 57168437 t fired, .
[[35mlola[0m][.] 70 EF STEQ 720/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 638
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 275/284 313/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 25811651 m, 90543 m/sec, 58251479 t fired, .
[[35mlola[0m][.] 70 EF STEQ 725/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 643
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 280/284 317/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 26173953 m, 72460 m/sec, 59403954 t fired, .
[[35mlola[0m][.] 70 EF STEQ 730/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 647
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 31 (type EXCL) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 70 EF STEQ 735/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 653
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 284 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 PolyORBLF-COL-S06J06T06-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 2845 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] CANCELED task # 31 (type EXCL) for PolyORBLF-COL-S06J06T06-CTLFireability-2024-10 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 5/284 5/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 453776 m, 90755 m/sec, 1058486 t fired, .
[[35mlola[0m][.] 70 EF STEQ 740/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 662
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 10/284 11/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 923880 m, 94020 m/sec, 2162873 t fired, .
[[35mlola[0m][.] 70 EF STEQ 745/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 664
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 15/284 16/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 1388221 m, 92868 m/sec, 3259010 t fired, .
[[35mlola[0m][.] 70 EF STEQ 750/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 669
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 20/284 21/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 1857718 m, 93899 m/sec, 4381104 t fired, .
[[35mlola[0m][.] 70 EF STEQ 755/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 674
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 25/284 26/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 2332753 m, 95007 m/sec, 5514234 t fired, .
[[35mlola[0m][.] 70 EF STEQ 760/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 679
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 30/284 31/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 2803916 m, 94232 m/sec, 6635521 t fired, .
[[35mlola[0m][.] 70 EF STEQ 765/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 684
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 35/284 36/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 3267495 m, 92715 m/sec, 7751576 t fired, .
[[35mlola[0m][.] 70 EF STEQ 770/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 689
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 40/284 40/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 3704379 m, 87376 m/sec, 8823333 t fired, .
[[35mlola[0m][.] 70 EF STEQ 775/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 693
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 45/284 45/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 4117890 m, 82702 m/sec, 9827204 t fired, .
[[35mlola[0m][.] 70 EF STEQ 780/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 698
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 50/284 49/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 4530511 m, 82524 m/sec, 10833008 t fired, .
[[35mlola[0m][.] 70 EF STEQ 785/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 702
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 55/284 53/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 4939331 m, 81764 m/sec, 11840926 t fired, .
[[35mlola[0m][.] 70 EF STEQ 790/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 706
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 60/284 57/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 5328580 m, 77849 m/sec, 12806149 t fired, .
[[35mlola[0m][.] 70 EF STEQ 795/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 710
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 65/284 60/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 5529812 m, 40246 m/sec, 13297253 t fired, .
[[35mlola[0m][.] 70 EF STEQ 800/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 713
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 70/284 60/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 5570818 m, 8201 m/sec, 13403837 t fired, .
[[35mlola[0m][.] 70 EF STEQ 805/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 713
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 76/284 60/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 5583536 m, 2543 m/sec, 13434108 t fired, .
[[35mlola[0m][.] 70 EF STEQ 811/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 831 secs. Pages in use: 713
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 81/284 60/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 5615848 m, 6462 m/sec, 13511341 t fired, .
[[35mlola[0m][.] 70 EF STEQ 816/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 836 secs. Pages in use: 713
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 87/284 61/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 5655812 m, 7992 m/sec, 13611740 t fired, .
[[35mlola[0m][.] 70 EF STEQ 822/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 842 secs. Pages in use: 714
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 93/284 61/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 5670935 m, 3024 m/sec, 13649188 t fired, .
[[35mlola[0m][.] 70 EF STEQ 828/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 848 secs. Pages in use: 714
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 122/284 61/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 5686196 m, 3052 m/sec, 13689127 t fired, .
[[35mlola[0m][.] 70 EF STEQ 858/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 714
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-01: AG false findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-02: EF true findpath[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S06J06T06-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S06J06T06-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-11: DISJ 0 2 1 0 5 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S06J06T06-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 177/284 61/2000 PolyORBLF-COL-S06J06T06-CTLFireability-2024-06 5687747 m, 310 m/sec, 13693835 t fired, .
[[35mlola[0m][.] 70 EF STEQ 915/3580 0/5 PolyORBLF-COL-S06J06T06-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 938 secs. Pages in use: 714
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 419 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PolyORBLF-COL-S06J06T06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PolyORBLF-COL-S06J06T06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r291-tajo-171654447800202"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PolyORBLF-COL-S06J06T06.tgz
mv PolyORBLF-COL-S06J06T06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;