About the Execution of LoLA for PolyORBLF-COL-S04J04T10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 0.000 | 782905.00 | 0.00 | 0.00 | ??F??????F??TT?F | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r291-tajo-171654447600138.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PolyORBLF-COL-S04J04T10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r291-tajo-171654447600138
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 608K
-rw-r--r-- 1 mcc users 10K Apr 11 17:13 CTLCardinality.txt
-rw-r--r-- 1 mcc users 94K Apr 11 17:13 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Apr 11 17:11 CTLFireability.txt
-rw-r--r-- 1 mcc users 67K Apr 11 17:11 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K Apr 23 07:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Apr 23 07:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 23 07:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 11 17:35 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 98K Apr 11 17:35 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Apr 11 17:32 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 52K Apr 11 17:32 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 07:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 10 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 154K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-00
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-01
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-02
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-03
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-04
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-05
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-06
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-07
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-08
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-09
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-10
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-11
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-12
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-13
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-14
FORMULA_NAME PolyORBLF-COL-S04J04T10-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717052446098
FORMULA PolyORBLF-COL-S04J04T10-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-COL-S04J04T10-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-COL-S04J04T10-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-COL-S04J04T10-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PolyORBLF-COL-S04J04T10-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717053229003
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Places: 870, Transitions: 5034
[[35mlola[0m][I] LAUNCH task # 51 (type SKEL/EQUN) for 39 PolyORBLF-COL-S04J04T10-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 49 (type SKEL/SRCH) for 39 PolyORBLF-COL-S04J04T10-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 49 (type SKEL/SRCH) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 16
[[35mlola[0m][I] fired transitions : 15
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 51 (type EQUN) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][W] findlow criterion violated for transition 59
[[35mlola[0m][I] FINISHED task # 51 (type SKEL/EQUN) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][W] findlow criterion violated for transition 38
[[35mlola[0m][W] findlow criterion violated for transition 60
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][W] findlow criterion violated for transition 4
[[35mlola[0m][W] findlow criterion violated for transition 23
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 PolyORBLF-COL-S04J04T10-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 969
[[35mlola[0m][I] fired transitions : 3284
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 PolyORBLF-COL-S04J04T10-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][W] findlow criterion violated for transition 9
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 39 PolyORBLF-COL-S04J04T10-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 0 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 3/224 1/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-02 70845 m, 14169 m/sec, 381197 t fired, .
[[35mlola[0m][.] 54 EF STEQ 0/3594 0/5 PolyORBLF-COL-S04J04T10-CTLFireability-2024-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][W] findlow criterion violated for 16 clusters
[[35mlola[0m][I] Time for checking findlow: 6
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 8/239 4/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-02 282693 m, 42369 m/sec, 1532633 t fired, .
[[35mlola[0m][.] 54 EF STEQ 5/3594 0/5 PolyORBLF-COL-S04J04T10-CTLFireability-2024-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 13/239 7/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-02 446760 m, 32813 m/sec, 2432110 t fired, .
[[35mlola[0m][.] 54 EF STEQ 10/3594 0/5 PolyORBLF-COL-S04J04T10-CTLFireability-2024-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 18/239 10/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-02 679631 m, 46574 m/sec, 3702328 t fired, .
[[35mlola[0m][.] 54 EF STEQ 15/3594 0/5 PolyORBLF-COL-S04J04T10-CTLFireability-2024-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 23/239 13/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-02 899186 m, 43911 m/sec, 4894303 t fired, .
[[35mlola[0m][.] 54 EF STEQ 20/3594 0/5 PolyORBLF-COL-S04J04T10-CTLFireability-2024-13 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1096732
[[35mlola[0m][I] fired transitions : 6005392
[[35mlola[0m][I] time used : 27
[[35mlola[0m][I] memory pages used : 16
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 39 PolyORBLF-COL-S04J04T10-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 255 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 43
[[35mlola[0m][I] fired transitions : 42
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 54 (type EQUN) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 PolyORBLF-COL-S04J04T10-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 274 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 38668
[[35mlola[0m][I] fired transitions : 42297
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 297 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 0/297 1/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 20310 m, 4062 m/sec, 31907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 5/297 6/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 363311 m, 68600 m/sec, 869094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 10/297 10/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 629100 m, 53157 m/sec, 1530625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 15/297 15/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 945477 m, 63275 m/sec, 2317137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 20/297 21/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 1379022 m, 86709 m/sec, 3391663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 25/297 28/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 1799295 m, 84054 m/sec, 4463127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 30/297 32/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 2151898 m, 70520 m/sec, 5575379 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 35/297 36/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 2508138 m, 71248 m/sec, 6692094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 40/297 41/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 2853947 m, 69161 m/sec, 7796528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 45/297 45/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 3206539 m, 70518 m/sec, 8904269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 50/297 49/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 3548936 m, 68479 m/sec, 10011082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 55/297 53/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 3902390 m, 70690 m/sec, 11121823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 60/297 56/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 4210495 m, 61621 m/sec, 12148992 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 65/297 61/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 4529650 m, 63831 m/sec, 13198852 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 70/297 65/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 4869048 m, 67879 m/sec, 14263146 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 75/297 69/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 5213154 m, 68821 m/sec, 15372535 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 80/297 73/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 5561392 m, 69647 m/sec, 16473914 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 85/297 76/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 5901163 m, 67954 m/sec, 17573398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 90/297 80/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 6251305 m, 70028 m/sec, 18674604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 95/297 85/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 6598466 m, 69432 m/sec, 19766999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 100/297 88/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 6891203 m, 58547 m/sec, 20783407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 105/297 92/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 7234936 m, 68746 m/sec, 21869966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 110/297 96/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 7563335 m, 65679 m/sec, 22929650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 115/297 100/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 7846077 m, 56548 m/sec, 23816213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 120/297 104/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 8192951 m, 69374 m/sec, 24901931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 125/297 108/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 8508563 m, 63122 m/sec, 25918301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 130/297 112/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 8850197 m, 68326 m/sec, 26990816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 135/297 115/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 9139003 m, 57761 m/sec, 27958890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 140/297 119/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 9454682 m, 63135 m/sec, 28998284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 145/297 122/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 9728104 m, 54684 m/sec, 29857997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 150/297 124/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 9887603 m, 31899 m/sec, 30365784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 155/297 125/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 10033380 m, 29155 m/sec, 30855587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 160/297 128/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 10197886 m, 32901 m/sec, 31363245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 165/297 129/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 10362368 m, 32896 m/sec, 31892520 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 170/297 132/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 10530961 m, 33718 m/sec, 32410075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 175/297 134/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 10774559 m, 48719 m/sec, 33200481 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 180/297 138/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 11072329 m, 59554 m/sec, 34139337 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 185/297 142/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 11373328 m, 60199 m/sec, 35084592 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 190/297 145/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 11665866 m, 58507 m/sec, 36119169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 195/297 148/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 11916896 m, 50206 m/sec, 37148845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 200/297 152/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 12183189 m, 53258 m/sec, 38078805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 205/297 155/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 12482776 m, 59917 m/sec, 39027025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 210/297 158/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 12780716 m, 59588 m/sec, 39974314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 215/297 163/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 13087020 m, 61260 m/sec, 40949117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 220/297 167/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 13436802 m, 69956 m/sec, 42045250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 225/297 171/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 13775467 m, 67733 m/sec, 43137338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 230/297 175/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 14121856 m, 69277 m/sec, 44224931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 235/297 178/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 14438548 m, 63338 m/sec, 45303117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 240/297 183/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 14773943 m, 67079 m/sec, 46387672 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 245/297 187/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 15124217 m, 70054 m/sec, 47483879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 250/297 191/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 15464621 m, 68080 m/sec, 48578763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 255/297 195/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 15813196 m, 69715 m/sec, 49677026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 260/297 199/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 16152937 m, 67948 m/sec, 50775511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 265/297 203/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 16502104 m, 69833 m/sec, 51874078 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 270/297 207/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 16843962 m, 68371 m/sec, 52969074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 275/297 211/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 17165403 m, 64288 m/sec, 54057504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 280/297 215/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 17514247 m, 69768 m/sec, 55155234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 285/297 219/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 17852079 m, 67566 m/sec, 56251259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 290/297 223/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 18198695 m, 69323 m/sec, 57342028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 295/297 226/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 18519029 m, 64066 m/sec, 58370741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 43 (type EXCL) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 PolyORBLF-COL-S04J04T10-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 297 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 PolyORBLF-COL-S04J04T10-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 3269 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 573
[[35mlola[0m][I] fired transitions : 1146
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 43 (type EXCL) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-14 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 5/326 4/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 199972 m, 39994 m/sec, 379962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 10/326 7/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 402474 m, 40500 m/sec, 807797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 15/326 10/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 600929 m, 39691 m/sec, 1238706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 20/326 13/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 794074 m, 38629 m/sec, 1645494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 25/326 16/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 989463 m, 39077 m/sec, 2060969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 30/326 19/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 1181657 m, 38438 m/sec, 2478915 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 35/326 24/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 1532140 m, 70096 m/sec, 3231969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 40/326 31/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 1945329 m, 82637 m/sec, 4106576 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 45/326 37/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 2359273 m, 82788 m/sec, 4992229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 301
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 50/326 42/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 2724252 m, 72995 m/sec, 5986965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 308
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 55/326 46/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 3066400 m, 68429 m/sec, 7028163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 60/326 50/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 3393396 m, 65399 m/sec, 8065686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 319
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 65/326 54/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 3731001 m, 67521 m/sec, 9091698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 325
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 70/326 59/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 4075709 m, 68941 m/sec, 10121786 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 75/326 63/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 4408332 m, 66524 m/sec, 11147486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 337
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 80/326 67/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 4746360 m, 67605 m/sec, 12174686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 85/326 70/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 5056096 m, 61947 m/sec, 13206185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 90/326 75/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 5386226 m, 66026 m/sec, 14231303 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 95/326 79/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 5725609 m, 67876 m/sec, 15260951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 361
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 100/326 81/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 5963328 m, 47543 m/sec, 16030258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 366
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 105/326 84/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 6130034 m, 33341 m/sec, 16516252 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 373
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 110/326 85/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 6284177 m, 30828 m/sec, 16996376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 115/326 89/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 6562999 m, 55764 m/sec, 17828619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 386
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 120/326 92/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 6843511 m, 56102 m/sec, 18720198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 392
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 125/326 96/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 7132522 m, 57802 m/sec, 19599138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 400
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 130/326 99/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 7427435 m, 58982 m/sec, 20473281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 407
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 135/326 102/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 7674927 m, 49498 m/sec, 21346190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 140/326 106/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 8003210 m, 65656 m/sec, 22345516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 421
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 145/326 110/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 8317769 m, 62911 m/sec, 23292826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 429
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 150/326 114/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 8638003 m, 64046 m/sec, 24301217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 437
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 155/326 118/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 8962525 m, 64904 m/sec, 25297074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 491 secs. Pages in use: 445
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 160/326 122/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 9292856 m, 66066 m/sec, 26293751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 496 secs. Pages in use: 452
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 165/326 126/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 9619231 m, 65275 m/sec, 27291706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 501 secs. Pages in use: 460
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 170/326 128/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 9850845 m, 46322 m/sec, 28010283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 506 secs. Pages in use: 466
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 175/326 132/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 10141591 m, 58149 m/sec, 28897506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 511 secs. Pages in use: 472
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 180/326 136/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 10433633 m, 58408 m/sec, 29888717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 516 secs. Pages in use: 480
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 185/326 140/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 10767222 m, 66717 m/sec, 30907130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 521 secs. Pages in use: 488
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 190/326 143/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 11099050 m, 66365 m/sec, 31928200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 526 secs. Pages in use: 496
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 195/326 148/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 11426548 m, 65499 m/sec, 32922740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 531 secs. Pages in use: 505
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 200/326 152/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 11764976 m, 67685 m/sec, 33942397 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 536 secs. Pages in use: 512
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 205/326 156/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 12087814 m, 64567 m/sec, 34963418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 541 secs. Pages in use: 520
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 210/326 159/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 12421126 m, 66662 m/sec, 35980235 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 546 secs. Pages in use: 527
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 215/326 163/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 12726186 m, 61012 m/sec, 36904916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 551 secs. Pages in use: 536
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 220/326 166/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 12990185 m, 52799 m/sec, 37946516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 556 secs. Pages in use: 542
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 225/326 169/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 13208402 m, 43643 m/sec, 38840096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 561 secs. Pages in use: 548
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 230/326 173/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 13479633 m, 54246 m/sec, 39668904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 566 secs. Pages in use: 555
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 235/326 177/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 13799677 m, 64008 m/sec, 40645177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 571 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 240/326 180/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 14054803 m, 51025 m/sec, 41459858 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 576 secs. Pages in use: 568
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 245/326 183/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 14305201 m, 50079 m/sec, 42199471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 581 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 250/326 187/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 14638326 m, 66625 m/sec, 43216391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 586 secs. Pages in use: 583
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 255/326 191/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 14957844 m, 63903 m/sec, 44227747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 591 secs. Pages in use: 591
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 260/326 195/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 15289379 m, 66307 m/sec, 45239181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 596 secs. Pages in use: 598
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 265/326 199/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 15626074 m, 67339 m/sec, 46242956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 601 secs. Pages in use: 606
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 270/326 202/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 15916557 m, 58096 m/sec, 47246394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 606 secs. Pages in use: 614
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 275/326 206/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 16239756 m, 64639 m/sec, 48237322 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 611 secs. Pages in use: 622
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 280/326 210/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 16570383 m, 66125 m/sec, 49230143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 616 secs. Pages in use: 630
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 285/326 214/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 16877055 m, 61334 m/sec, 50174524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 621 secs. Pages in use: 637
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 290/326 218/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 17208434 m, 66275 m/sec, 51182308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 626 secs. Pages in use: 645
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 295/326 222/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 17528251 m, 63963 m/sec, 52195790 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages in use: 653
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 300/326 226/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 17855818 m, 65513 m/sec, 53187411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 636 secs. Pages in use: 662
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 305/326 229/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 18135200 m, 55876 m/sec, 54011934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 641 secs. Pages in use: 668
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 310/326 232/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 18352192 m, 43398 m/sec, 54750048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 646 secs. Pages in use: 674
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 315/326 236/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 18640209 m, 57603 m/sec, 55665740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 651 secs. Pages in use: 682
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 320/326 239/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 18961056 m, 64169 m/sec, 56643293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 656 secs. Pages in use: 689
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 325/326 243/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 19279248 m, 63638 m/sec, 57651191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 661 secs. Pages in use: 697
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 34 (type EXCL) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 666 secs. Pages in use: 705
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 PolyORBLF-COL-S04J04T10-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 2934 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] CANCELED task # 34 (type EXCL) for PolyORBLF-COL-S04J04T10-CTLFireability-2024-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 5/326 6/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 384251 m, 76850 m/sec, 427031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 671 secs. Pages in use: 718
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 10/326 16/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 1100784 m, 143306 m/sec, 1243742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 676 secs. Pages in use: 728
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 15/326 27/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 1806738 m, 141190 m/sec, 2056956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 681 secs. Pages in use: 743
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 20/326 37/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 2513021 m, 141256 m/sec, 2864495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 686 secs. Pages in use: 756
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 25/326 46/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 3194631 m, 136322 m/sec, 3659741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 691 secs. Pages in use: 769
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 30/326 56/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 3863066 m, 133687 m/sec, 4445037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 696 secs. Pages in use: 783
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 35/326 65/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 4525393 m, 132465 m/sec, 5232720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 701 secs. Pages in use: 796
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 40/326 74/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 5181843 m, 131290 m/sec, 6019323 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 706 secs. Pages in use: 809
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 45/326 82/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 5725830 m, 108797 m/sec, 6673374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 711 secs. Pages in use: 820
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 50/326 90/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 6333718 m, 121577 m/sec, 7403522 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 716 secs. Pages in use: 832
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 55/326 98/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 6926052 m, 118466 m/sec, 8115492 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 721 secs. Pages in use: 844
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 60/326 107/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 7518053 m, 118400 m/sec, 8832707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 726 secs. Pages in use: 856
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 65/326 115/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 8110625 m, 118514 m/sec, 9565550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 731 secs. Pages in use: 867
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 70/326 123/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 8755968 m, 129068 m/sec, 10344964 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 736 secs. Pages in use: 879
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 75/326 133/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 9411541 m, 131114 m/sec, 11133256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 741 secs. Pages in use: 892
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 80/326 141/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 10021365 m, 121964 m/sec, 11896153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 746 secs. Pages in use: 904
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 85/326 149/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 10646216 m, 124970 m/sec, 12674288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 751 secs. Pages in use: 916
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 90/326 157/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 11241448 m, 119046 m/sec, 13410473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 756 secs. Pages in use: 928
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 95/326 166/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 11842290 m, 120168 m/sec, 14148866 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 761 secs. Pages in use: 941
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 100/326 171/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 12258844 m, 83310 m/sec, 14671280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 766 secs. Pages in use: 949
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 105/326 172/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 12341027 m, 16436 m/sec, 14774655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 771 secs. Pages in use: 951
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPolyORBLF-COL-S04J04T10-CTLFireability-2024-13: EXEF true state space /EXEF[0m
[[35mlola[0m][.] [1m[31mPolyORBLF-COL-S04J04T10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PolyORBLF-COL-S04J04T10-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 111/326 172/2000 PolyORBLF-COL-S04J04T10-CTLFireability-2024-10 12354854 m, 2765 m/sec, 14792560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 951
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 410 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PolyORBLF-COL-S04J04T10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PolyORBLF-COL-S04J04T10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r291-tajo-171654447600138"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PolyORBLF-COL-S04J04T10.tgz
mv PolyORBLF-COL-S04J04T10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;