About the Execution of LoLA for PhaseVariation-PT-D10CS010
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16037.140 | 3600000.00 | 6787706.00 | 11874.70 | ?????????F???T?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408600330.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PhaseVariation-PT-D10CS010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408600330
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.4M
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 98K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.9K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.0K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 19 18:45 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.4K Apr 11 21:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 52K Apr 11 21:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 17K Apr 11 21:03 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Apr 11 21:03 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 9 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 2.9M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-00
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-01
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-02
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-03
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-04
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-05
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-06
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-07
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-08
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-09
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-10
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2024-11
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2023-12
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2023-13
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2023-14
FORMULA_NAME PhaseVariation-PT-D10CS010-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717177635190
FORMULA PhaseVariation-PT-D10CS010-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PhaseVariation-PT-D10CS010-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 52 (type CNST) for 51 PhaseVariation-PT-D10CS010-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 52 (type CNST) for PhaseVariation-PT-D10CS010-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Rule S: 52 transitions removed,2 places removed
[[35mlola[0m][I] LAUNCH task # 72 (type CNST) for 71 PhaseVariation-PT-D10CS010-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 72 (type CNST) for PhaseVariation-PT-D10CS010-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D10CS010-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D10CS010-CTLFireability-2023-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-03: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-05: DISJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-07: DISJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-10: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2023-15: SP ECTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 81 (type EXCL) for 37 PhaseVariation-PT-D10CS010-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 84 (type EQUN) for 37 PhaseVariation-PT-D10CS010-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 86 (type EQUN) for 37 PhaseVariation-PT-D10CS010-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 84 (type EQUN) for PhaseVariation-PT-D10CS010-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 81 (type EXCL) for PhaseVariation-PT-D10CS010-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 101
[[35mlola[0m][I] fired transitions : 100
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 86 (type EQUN) for PhaseVariation-PT-D10CS010-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 86 (type EQUN) for PhaseVariation-PT-D10CS010-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 PhaseVariation-PT-D10CS010-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 93 (type EQUN) for 19 PhaseVariation-PT-D10CS010-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 95 (type EQUN) for 19 PhaseVariation-PT-D10CS010-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 95 (type EQUN) for PhaseVariation-PT-D10CS010-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 101 (type EQUN) for 37 PhaseVariation-PT-D10CS010-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 93 (type EQUN) for PhaseVariation-PT-D10CS010-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 102 (type FNDP) for 19 PhaseVariation-PT-D10CS010-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 103 (type EQUN) for 19 PhaseVariation-PT-D10CS010-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 101 (type EQUN) for PhaseVariation-PT-D10CS010-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 102 (type FNDP) for PhaseVariation-PT-D10CS010-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 103 (type EQUN) for PhaseVariation-PT-D10CS010-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][I] FINISHED task # 103 (type EQUN) for PhaseVariation-PT-D10CS010-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D10CS010-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D10CS010-CTLFireability-2023-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-05: DISJ 0 1 0 0 8 0 0 3
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-07: DISJ 0 2 0 0 7 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2023-15: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 3/199 1/2000 PhaseVariation-PT-D10CS010-CTLFireability-2024-00 41991 m, 8398 m/sec, 833270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D10CS010-CTLFireability-2024-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D10CS010-CTLFireability-2023-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-05: DISJ 0 1 0 0 8 0 0 3
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-07: DISJ 0 2 0 0 7 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D10CS010-CTLFireability-2023-15: SP ECTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 8/199 1/2000 PhaseVariation-PT-D10CS010-CTLFireability-2024-00 128786 m, 17359 m/sec, 2872913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 1
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[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for PhaseVariation-PT-D10CS010-CTLFireability-2024-05
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[[35mlola[0m][.] 17 CTL EXCL 15/311 2/2000 PhaseVariation-PT-D10CS010-CTLFireability-2024-04 219408 m, 14004 m/sec, 5061855 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PhaseVariation-PT-D10CS010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PhaseVariation-PT-D10CS010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408600330"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PhaseVariation-PT-D10CS010.tgz
mv PhaseVariation-PT-D10CS010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;