About the Execution of LoLA for PhaseVariation-PT-D05CS100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.500 | 2011899.00 | 2081530.00 | 6583.20 | ????F??????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408600324.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PhaseVariation-PT-D05CS100, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408600324
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 101K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 69K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K May 19 07:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:45 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 11 20:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Apr 11 20:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 16K Apr 11 20:52 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 90K Apr 11 20:52 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 9 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 633K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-00
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-01
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-02
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-03
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-04
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-05
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-06
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-07
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-08
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-09
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-10
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-11
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-12
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-13
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-14
FORMULA_NAME PhaseVariation-PT-D05CS100-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717175608907
FORMULA PhaseVariation-PT-D05CS100-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717177620806
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 PhaseVariation-PT-D05CS100-LTLFireability-04
[[35mlola[0m][I] time limit : 150 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 126
[[35mlola[0m][I] fired transitions : 126
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 6 PhaseVariation-PT-D05CS100-LTLFireability-02
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 19 PhaseVariation-PT-D05CS100-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for PhaseVariation-PT-D05CS100-LTLFireability-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 5/189 2/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 162904 m, 32580 m/sec, 3111302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 10/189 3/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 346912 m, 36801 m/sec, 6633343 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 15/189 4/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 523472 m, 35312 m/sec, 10129771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 20/189 5/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 660977 m, 27501 m/sec, 13545117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 25/189 6/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 790367 m, 25878 m/sec, 17109111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 30/189 7/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 952581 m, 32442 m/sec, 20565945 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 35/189 8/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1124182 m, 34320 m/sec, 23969847 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 40/189 9/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1254973 m, 26158 m/sec, 27510168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 45/189 10/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1381965 m, 25398 m/sec, 30989766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 50/189 11/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1512923 m, 26191 m/sec, 34520011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 55/189 11/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1641032 m, 25621 m/sec, 38006248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 60/189 13/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1814872 m, 34768 m/sec, 41518945 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 65/189 14/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1982088 m, 33443 m/sec, 45023952 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 70/189 15/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2111075 m, 25797 m/sec, 48561497 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 75/189 15/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2241159 m, 26016 m/sec, 52036234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 80/189 16/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2369372 m, 25642 m/sec, 55526405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 85/189 17/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2494622 m, 25050 m/sec, 58969457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 90/189 18/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2626831 m, 26441 m/sec, 62540686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 95/189 19/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2756310 m, 25895 m/sec, 66057748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 100/189 20/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2935038 m, 35745 m/sec, 69541642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 105/189 21/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3106811 m, 34354 m/sec, 73018725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 110/189 22/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3242904 m, 27218 m/sec, 76589558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 115/189 23/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3385773 m, 28573 m/sec, 80098565 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 120/189 24/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3517727 m, 26390 m/sec, 83565689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 125/189 25/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3656496 m, 27753 m/sec, 87001461 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 130/189 26/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3789191 m, 26539 m/sec, 90448537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 135/189 27/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3926546 m, 27471 m/sec, 93873901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 140/189 28/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4063026 m, 27296 m/sec, 97397922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 145/189 28/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4209189 m, 29232 m/sec, 100872003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 150/189 30/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4371259 m, 32414 m/sec, 104381993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 155/189 31/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4521921 m, 30132 m/sec, 107868584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 160/189 31/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4655815 m, 26778 m/sec, 111388940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 165/189 32/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4801871 m, 29211 m/sec, 114856752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 170/189 33/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4931511 m, 25928 m/sec, 118342296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 175/189 34/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 5085567 m, 30811 m/sec, 121773625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 180/189 35/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 5220662 m, 27019 m/sec, 125192260 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 185/189 36/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 5355404 m, 26948 m/sec, 128619889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 11 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 1 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 61 PhaseVariation-PT-D05CS100-LTLFireability-15
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 6 PhaseVariation-PT-D05CS100-LTLFireability-02
[[35mlola[0m][I] time limit : 3410 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 5/3410 2/5 PhaseVariation-PT-D05CS100-LTLFireability-02 186123 m, -1033856 m/sec, 3593644 t fired, .
[[35mlola[0m][.] 62 LTL EXCL 5/189 2/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 186464 m, 37292 m/sec, 3600116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 10/3410 3/5 PhaseVariation-PT-D05CS100-LTLFireability-02 371989 m, 37173 m/sec, 7098009 t fired, .
[[35mlola[0m][.] 62 LTL EXCL 10/179 3/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 372671 m, 37241 m/sec, 7112375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 15/3410 4/5 PhaseVariation-PT-D05CS100-LTLFireability-02 545299 m, 34662 m/sec, 10558912 t fired, .
[[35mlola[0m][.] 62 LTL EXCL 15/179 4/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 546202 m, 34706 m/sec, 10577674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 20/3410 5/5 PhaseVariation-PT-D05CS100-LTLFireability-02 681182 m, 27176 m/sec, 14150847 t fired, .
[[35mlola[0m][.] 62 LTL EXCL 20/179 5/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 681906 m, 27140 m/sec, 14170697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 11 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 25/179 6/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 812726 m, 26164 m/sec, 17716130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 30/189 7/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 985108 m, 34476 m/sec, 21173755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 35/189 8/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 1149006 m, 32779 m/sec, 24611980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 40/189 9/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 1277648 m, 25728 m/sec, 28138931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 45/189 10/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 1407928 m, 26056 m/sec, 31618482 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 50/189 11/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 1538107 m, 26035 m/sec, 35164638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 55/189 12/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 1664078 m, 25194 m/sec, 38632239 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 60/189 13/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 1845734 m, 36331 m/sec, 42158095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 65/189 14/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 2006823 m, 32217 m/sec, 45671182 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 70/189 15/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 2133883 m, 25412 m/sec, 49208936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 75/189 16/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 2266457 m, 26514 m/sec, 52706905 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 80/189 16/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 2392469 m, 25202 m/sec, 56181657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 85/189 17/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 2522047 m, 25915 m/sec, 59624818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 90/189 18/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 2652345 m, 26059 m/sec, 63191235 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 95/189 19/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 2779539 m, 25438 m/sec, 66673053 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 100/189 20/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 2964715 m, 37035 m/sec, 70135261 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 105/189 21/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 3129164 m, 32889 m/sec, 73635222 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 110/189 22/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 3266260 m, 27419 m/sec, 77178942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 115/189 23/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 3406358 m, 28019 m/sec, 80673297 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 120/189 24/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 3540150 m, 26758 m/sec, 84134971 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 125/189 25/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 3678457 m, 27661 m/sec, 87566951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 130/189 26/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 3809634 m, 26235 m/sec, 90997580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 135/189 27/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 3950010 m, 28075 m/sec, 94441224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 140/189 28/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 4083053 m, 26608 m/sec, 97932854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 145/189 29/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 4235035 m, 30396 m/sec, 101386921 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 150/189 30/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 4390146 m, 31022 m/sec, 104898490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 155/189 31/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 4539852 m, 29941 m/sec, 108364851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 160/189 32/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 4679508 m, 27931 m/sec, 111857209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 165/189 33/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 4820013 m, 28101 m/sec, 115320489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 170/189 33/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 4942158 m, 24429 m/sec, 118631789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 175/189 34/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 5095717 m, 30711 m/sec, 122049322 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 180/189 35/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 5230716 m, 26999 m/sec, 125443419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 185/189 36/2000 PhaseVariation-PT-D05CS100-LTLFireability-15 5367320 m, 27320 m/sec, 128868098 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 62 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-14: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 50 PhaseVariation-PT-D05CS100-LTLFireability-14
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 61 PhaseVariation-PT-D05CS100-LTLFireability-15
[[35mlola[0m][I] time limit : 3220 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 126
[[35mlola[0m][I] fired transitions : 126
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 5/214 2/5 PhaseVariation-PT-D05CS100-LTLFireability-15 173462 m, -1038771 m/sec, 3331180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 10/214 3/5 PhaseVariation-PT-D05CS100-LTLFireability-15 357770 m, 36861 m/sec, 6876283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 15/214 4/5 PhaseVariation-PT-D05CS100-LTLFireability-15 536362 m, 35718 m/sec, 10385295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 20/214 5/5 PhaseVariation-PT-D05CS100-LTLFireability-15 675770 m, 27881 m/sec, 13987523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 62 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 PhaseVariation-PT-D05CS100-LTLFireability-12
[[35mlola[0m][I] time limit : 228 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 126
[[35mlola[0m][I] fired transitions : 126
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 PhaseVariation-PT-D05CS100-LTLFireability-09
[[35mlola[0m][I] time limit : 245 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 129
[[35mlola[0m][I] fired transitions : 130
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 PhaseVariation-PT-D05CS100-LTLFireability-08
[[35mlola[0m][I] time limit : 266 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 126
[[35mlola[0m][I] fired transitions : 126
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 PhaseVariation-PT-D05CS100-LTLFireability-07
[[35mlola[0m][I] time limit : 290 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 5/290 2/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 185418 m, 37083 m/sec, 3362946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 10/290 3/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 360456 m, 35007 m/sec, 6943868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 15/290 4/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 541034 m, 36115 m/sec, 10464541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 20/290 5/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 730700 m, 37933 m/sec, 13976666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 25/290 6/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 904488 m, 34757 m/sec, 17475440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 30/290 8/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 1081002 m, 35302 m/sec, 20926645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 35/290 9/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 1229565 m, 29712 m/sec, 24505732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 40/290 9/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 1355502 m, 25187 m/sec, 28092474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 45/290 10/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 1485346 m, 25968 m/sec, 31641799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 50/290 11/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 1615764 m, 26083 m/sec, 35183576 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 55/290 12/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 1784380 m, 33723 m/sec, 38616263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 60/290 13/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 1955225 m, 34169 m/sec, 42058217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 65/290 14/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 2126384 m, 34231 m/sec, 45446819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 70/290 16/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 2284058 m, 31534 m/sec, 48801739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 75/290 16/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 2412604 m, 25709 m/sec, 52273884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 80/290 17/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 2536022 m, 24683 m/sec, 55734392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 85/290 18/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 2660462 m, 24888 m/sec, 59164313 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 90/290 19/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 2783977 m, 24703 m/sec, 62514190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 95/290 20/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 2917284 m, 26661 m/sec, 65974698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 100/290 20/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 3038604 m, 24264 m/sec, 69428056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 105/290 21/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 3164588 m, 25196 m/sec, 72836737 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 110/290 22/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 3289270 m, 24936 m/sec, 76217369 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 115/290 23/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 3457756 m, 33697 m/sec, 79612557 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 120/290 24/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 3630588 m, 34566 m/sec, 83055627 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 125/290 25/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 3800942 m, 34070 m/sec, 86454324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 130/290 26/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 3958060 m, 31423 m/sec, 89862603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 135/290 27/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 4087110 m, 25810 m/sec, 93352364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 140/290 28/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 4211151 m, 24808 m/sec, 96813410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 145/290 29/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 4336348 m, 25039 m/sec, 100241984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 150/290 30/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 4461442 m, 25018 m/sec, 103602661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 155/290 31/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 4590834 m, 25878 m/sec, 107021259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 160/290 31/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 4710763 m, 23985 m/sec, 110430034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 165/290 32/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 4835053 m, 24858 m/sec, 113789342 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 170/290 33/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 4959410 m, 24871 m/sec, 117129088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 175/290 34/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 5093358 m, 26789 m/sec, 120562288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 180/290 35/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 5219374 m, 25203 m/sec, 124051211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 185/290 36/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 5344376 m, 25000 m/sec, 127513139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 190/290 36/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 5469793 m, 25083 m/sec, 130935482 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 195/290 37/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 5620408 m, 30123 m/sec, 134301425 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 200/290 39/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 5795824 m, 35083 m/sec, 137725959 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 205/290 40/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 5974478 m, 35730 m/sec, 141111278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 210/290 41/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 6147203 m, 34545 m/sec, 144444926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 215/290 42/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 6286628 m, 27885 m/sec, 147960384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 220/290 43/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 6420602 m, 26794 m/sec, 151441883 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 225/290 44/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 6553752 m, 26630 m/sec, 154895736 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 230/290 44/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 6688922 m, 27034 m/sec, 158266067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 235/290 45/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 6824436 m, 27102 m/sec, 161682012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 240/290 46/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 6956818 m, 26476 m/sec, 165048539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 245/290 47/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 7085712 m, 25778 m/sec, 168409111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 250/290 48/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 7214338 m, 25725 m/sec, 171691645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 255/290 49/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 7355228 m, 28178 m/sec, 175089102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 260/290 50/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 7480776 m, 25109 m/sec, 178458638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 265/290 50/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 7611783 m, 26201 m/sec, 181794431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 270/290 51/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 7742420 m, 26127 m/sec, 185083449 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 275/290 52/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 7886704 m, 28856 m/sec, 188507972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 280/290 53/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 8015824 m, 25824 m/sec, 191980403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 285/290 54/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 8149076 m, 26650 m/sec, 195417100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 290/290 55/2000 PhaseVariation-PT-D05CS100-LTLFireability-07 8281055 m, 26395 m/sec, 198773582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 30 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-07 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 22 PhaseVariation-PT-D05CS100-LTLFireability-06
[[35mlola[0m][I] time limit : 290 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 PhaseVariation-PT-D05CS100-LTLFireability-07
[[35mlola[0m][I] time limit : 2900 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 27 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 126
[[35mlola[0m][I] fired transitions : 126
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 5/322 2/5 PhaseVariation-PT-D05CS100-LTLFireability-07 177642 m, -1620682 m/sec, 3244919 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 10/322 3/5 PhaseVariation-PT-D05CS100-LTLFireability-07 352388 m, 34949 m/sec, 6773061 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 15/322 4/5 PhaseVariation-PT-D05CS100-LTLFireability-07 529837 m, 35489 m/sec, 10234922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 LTL EXCL 20/322 5/5 PhaseVariation-PT-D05CS100-LTLFireability-07 712204 m, 36473 m/sec, 13684435 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 30 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-07 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 PhaseVariation-PT-D05CS100-LTLFireability-03
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 5/359 2/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 174510 m, 34902 m/sec, 3351283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 10/359 3/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 355743 m, 36246 m/sec, 6833599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 15/359 4/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 530674 m, 34986 m/sec, 10284395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 20/359 5/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 670209 m, 27907 m/sec, 13820930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 25/359 6/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 798780 m, 25714 m/sec, 17327602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 30/359 7/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 960279 m, 32299 m/sec, 20734431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 35/359 8/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 1129067 m, 33757 m/sec, 24075650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 40/359 9/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 1256703 m, 25527 m/sec, 27550111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 45/359 10/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 1380714 m, 24802 m/sec, 30954564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 50/359 11/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 1509589 m, 25775 m/sec, 34421170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 55/359 11/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 1635278 m, 25137 m/sec, 37838193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 60/359 12/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 1798986 m, 32741 m/sec, 41278903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 65/359 14/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 1970528 m, 34308 m/sec, 44683841 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 70/359 14/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 2097839 m, 25462 m/sec, 48186174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 75/359 15/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 2221361 m, 24704 m/sec, 51583450 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 80/359 16/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 2348914 m, 25510 m/sec, 55019734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 85/359 17/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 2468547 m, 23926 m/sec, 58255357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 90/359 18/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 2599289 m, 26148 m/sec, 61713900 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 95/359 19/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 2724808 m, 25103 m/sec, 65180817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 100/359 20/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 2885083 m, 32055 m/sec, 68582572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 105/359 21/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 3060017 m, 34986 m/sec, 71938704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 110/359 22/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 3199787 m, 27954 m/sec, 75452128 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 115/359 23/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 3332083 m, 26459 m/sec, 78864285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 120/359 24/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 3466355 m, 26854 m/sec, 82281873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 125/359 24/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 3598898 m, 26508 m/sec, 85624530 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 130/359 25/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 3733026 m, 26825 m/sec, 89015487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 135/359 26/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 3863207 m, 26036 m/sec, 92345675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 140/359 27/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 4000310 m, 27420 m/sec, 95770326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 145/359 28/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 4132600 m, 26458 m/sec, 99172709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 150/359 29/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 4294984 m, 32476 m/sec, 102557545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 155/359 30/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 4440495 m, 29102 m/sec, 105995393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 160/359 31/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 4578661 m, 27633 m/sec, 109389382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 165/359 32/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 4725280 m, 29323 m/sec, 112780243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 170/359 33/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 4851302 m, 25204 m/sec, 116175170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 175/359 34/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 4984200 m, 26579 m/sec, 119574431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 180/359 35/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 5130314 m, 29222 m/sec, 122909157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 185/359 35/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 5261056 m, 26148 m/sec, 126218126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 190/359 36/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 5400571 m, 27903 m/sec, 129582453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 195/359 37/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 5540198 m, 27925 m/sec, 132884556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 200/359 38/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 5673002 m, 26560 m/sec, 136160121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 205/359 39/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 5807651 m, 26929 m/sec, 139412396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 210/359 40/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 5979150 m, 34299 m/sec, 142841801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 215/359 41/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 6155342 m, 35238 m/sec, 146222812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 220/359 43/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 6324425 m, 33816 m/sec, 149573759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 225/359 44/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 6469149 m, 28944 m/sec, 152951949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 230/359 44/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 6593665 m, 24903 m/sec, 156365896 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 235/359 45/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 6739424 m, 29151 m/sec, 159691796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 240/359 46/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 6903419 m, 32799 m/sec, 162942294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 245/359 47/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 7041386 m, 27593 m/sec, 166253999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 250/359 48/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 7160829 m, 23888 m/sec, 169570932 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 255/359 49/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 7286081 m, 25050 m/sec, 172878424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 260/359 50/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 7406330 m, 24049 m/sec, 176221567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 265/359 51/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 7542742 m, 27282 m/sec, 179527617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 270/359 52/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 7712652 m, 33982 m/sec, 182888009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 275/359 53/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 7856671 m, 28803 m/sec, 186230357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 280/359 54/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 7978260 m, 24317 m/sec, 189587641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 285/359 54/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 8104829 m, 25313 m/sec, 192895248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 290/359 55/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 8224464 m, 23927 m/sec, 196210669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 295/359 56/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 8344842 m, 24075 m/sec, 199459946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 300/359 57/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 8469490 m, 24929 m/sec, 202867757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 305/359 58/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 8592296 m, 24561 m/sec, 206188091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 310/359 59/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 8762875 m, 34115 m/sec, 209505223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 315/359 60/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 8927680 m, 32961 m/sec, 212812268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 320/359 61/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 9060195 m, 26503 m/sec, 216230363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 325/359 62/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 9194719 m, 26904 m/sec, 219564800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 330/359 62/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 9323358 m, 25727 m/sec, 222896327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 335/359 63/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 9449601 m, 25248 m/sec, 226134826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 340/359 64/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 9578425 m, 25764 m/sec, 229428681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 345/359 65/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 9705842 m, 25483 m/sec, 232644045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 350/359 66/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 9838381 m, 26507 m/sec, 235973942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 355/359 67/2000 PhaseVariation-PT-D05CS100-LTLFireability-03 9966201 m, 25564 m/sec, 239249209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 14 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-03 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 9 (type EXCL) for 6 PhaseVariation-PT-D05CS100-LTLFireability-02
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 PhaseVariation-PT-D05CS100-LTLFireability-03
[[35mlola[0m][I] time limit : 2515 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 5/359 2/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 218745 m, 43749 m/sec, 3347975 t fired, .
[[35mlola[0m][.] 14 LTL EXCL 5/2515 2/5 PhaseVariation-PT-D05CS100-LTLFireability-03 177012 m, -1957837 m/sec, 3402828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 10/359 3/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 396755 m, 35602 m/sec, 6766830 t fired, .
[[35mlola[0m][.] 14 LTL EXCL 10/314 3/5 PhaseVariation-PT-D05CS100-LTLFireability-03 351429 m, 34883 m/sec, 6735108 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 15/359 4/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 573482 m, 35345 m/sec, 10069702 t fired, .
[[35mlola[0m][.] 14 LTL EXCL 15/314 4/5 PhaseVariation-PT-D05CS100-LTLFireability-03 518624 m, 33439 m/sec, 10031126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 20/359 5/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 739965 m, 33296 m/sec, 13438978 t fired, .
[[35mlola[0m][.] 14 LTL EXCL 20/314 5/5 PhaseVariation-PT-D05CS100-LTLFireability-03 655920 m, 27459 m/sec, 13389744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 14 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-03 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 25/359 7/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 921446 m, 36296 m/sec, 16763371 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 30/359 8/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1084060 m, 32522 m/sec, 20202650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 35/359 9/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1270749 m, 37337 m/sec, 23667564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 40/359 10/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1452791 m, 36408 m/sec, 27065562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 45/359 11/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1621722 m, 33786 m/sec, 30435639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 50/359 12/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1796578 m, 34971 m/sec, 33873709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 55/359 14/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 1983490 m, 37382 m/sec, 37288725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 60/359 15/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2163964 m, 36094 m/sec, 40640754 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 65/359 16/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2337484 m, 34704 m/sec, 43965334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 70/359 17/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2506101 m, 33723 m/sec, 47233425 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 75/359 19/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2723423 m, 43464 m/sec, 50579499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 80/359 20/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 2902203 m, 35756 m/sec, 54007934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 85/359 21/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3078913 m, 35342 m/sec, 57338717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 90/359 22/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3248008 m, 33819 m/sec, 60727773 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 95/359 23/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3429099 m, 36218 m/sec, 64073623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 100/359 24/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3585569 m, 31294 m/sec, 67386494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 105/359 25/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3764870 m, 35860 m/sec, 70725096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 110/359 27/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 3942226 m, 35471 m/sec, 74018761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 115/359 28/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4106773 m, 32909 m/sec, 77286891 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 120/359 29/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4272571 m, 33159 m/sec, 80590373 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 125/359 30/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4456391 m, 36764 m/sec, 83893128 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 130/359 31/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4624163 m, 33554 m/sec, 87131422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 135/359 32/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4789951 m, 33157 m/sec, 90342472 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 140/359 33/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 4959590 m, 33927 m/sec, 93492276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 145/359 34/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 5120573 m, 32196 m/sec, 96876251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 150/359 35/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 5271721 m, 30229 m/sec, 100273547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 155/359 36/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 5407891 m, 27234 m/sec, 103681576 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 160/359 37/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 5545060 m, 27433 m/sec, 107007811 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 165/359 38/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 5668537 m, 24695 m/sec, 110366341 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 170/359 39/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 5812370 m, 28766 m/sec, 113714260 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 175/359 40/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 5939008 m, 25327 m/sec, 117032112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 180/359 41/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 6059212 m, 24040 m/sec, 120298626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 185/359 42/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 6183435 m, 24844 m/sec, 123677081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 190/359 43/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 6334939 m, 30300 m/sec, 126982361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 195/359 43/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 6461874 m, 25387 m/sec, 130269889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 200/359 44/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 6588190 m, 25263 m/sec, 133521351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 205/359 45/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 6715691 m, 25500 m/sec, 136822294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 210/359 46/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 6853324 m, 27526 m/sec, 140188172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 215/359 47/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 6986699 m, 26675 m/sec, 143500889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 220/359 48/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 7117061 m, 26072 m/sec, 146760650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 225/359 49/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 7247451 m, 26078 m/sec, 149993877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 230/359 49/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 7377717 m, 26053 m/sec, 153194231 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 235/359 50/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 7499787 m, 24414 m/sec, 156355584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 240/359 52/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 7712936 m, 42629 m/sec, 159634264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 245/359 53/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 7885099 m, 34432 m/sec, 162966894 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 250/359 54/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 8060846 m, 35149 m/sec, 166186115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 255/359 55/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 8215290 m, 30888 m/sec, 169464923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 260/359 56/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 8402273 m, 37396 m/sec, 172713509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 265/359 57/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 8553089 m, 30163 m/sec, 175916009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 270/359 58/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 8713962 m, 32174 m/sec, 179176377 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 275/359 60/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 8895665 m, 36340 m/sec, 182331830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 280/359 61/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 9052650 m, 31397 m/sec, 185442112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 285/359 62/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 9213657 m, 32201 m/sec, 188617451 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 290/359 63/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 9386117 m, 34492 m/sec, 191838524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 295/359 64/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 9557478 m, 34272 m/sec, 194996223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 300/359 65/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 9720060 m, 32516 m/sec, 198119797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 305/359 66/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 9882494 m, 32486 m/sec, 201179616 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 264
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 310/359 67/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 10037322 m, 30965 m/sec, 204282467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 315/359 68/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 10192269 m, 30989 m/sec, 207601097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 320/359 69/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 10324150 m, 26376 m/sec, 210932519 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 325/359 70/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 10466324 m, 28434 m/sec, 214161438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 330/359 71/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 10588079 m, 24351 m/sec, 217399197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 335/359 72/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 10709526 m, 24289 m/sec, 220703200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 340/359 73/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 10856139 m, 29322 m/sec, 223972399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 345/359 73/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 10975608 m, 23893 m/sec, 227217508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 350/359 74/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 11093468 m, 23572 m/sec, 230420970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 LTL EXCL 355/359 75/2000 PhaseVariation-PT-D05CS100-LTLFireability-02 11220166 m, 25339 m/sec, 233690346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 9 (type EXCL) for PhaseVariation-PT-D05CS100-LTLFireability-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-02: CONJ 0 0 0 0 2 1 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PhaseVariation-PT-D05CS100"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PhaseVariation-PT-D05CS100, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408600324"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PhaseVariation-PT-D05CS100.tgz
mv PhaseVariation-PT-D05CS100 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;