About the Execution of LoLA for PhaseVariation-PT-D05CS100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 10017.808 | 3600000.00 | 3039759.00 | 13583.70 | ?T?????????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408600321.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PhaseVariation-PT-D05CS100, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408600321
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 101K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 69K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K May 19 07:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:45 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 11 20:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Apr 11 20:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 16K Apr 11 20:52 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 90K Apr 11 20:52 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 9 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 633K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-00
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-01
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-02
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-03
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-04
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-05
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-06
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-07
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-08
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-09
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-10
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2024-11
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2023-12
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2023-13
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2023-14
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLCardinality-2023-15
=== Now, execution of the tool begins
BK_START 1717170832841
FORMULA PhaseVariation-PT-D05CS100-CTLCardinality-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 PhaseVariation-PT-D05CS100-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 15 PhaseVariation-PT-D05CS100-CTLCardinality-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 55 (type EQUN) for 21 PhaseVariation-PT-D05CS100-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 54 (type EQUN) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 55 (type EQUN) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 5/239 1/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 174780 m, 34956 m/sec, 2932150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 9 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 10/239 2/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 365894 m, 38222 m/sec, 6639283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 14 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 15/239 3/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 544711 m, 35763 m/sec, 10313105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 19 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 20/239 4/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 695355 m, 30128 m/sec, 14062807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 24 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 25/239 4/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 828282 m, 26585 m/sec, 17779668 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 29 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 30/239 5/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 994916 m, 33326 m/sec, 21405265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 34 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 35/239 6/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 1168834 m, 34783 m/sec, 24951008 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 39 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 40/239 6/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 1300692 m, 26371 m/sec, 28638845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 44 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 45/239 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 1431286 m, 26118 m/sec, 32251911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 49 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 50/239 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 1566607 m, 27064 m/sec, 35964815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 54 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 55/239 8/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 1696590 m, 25996 m/sec, 39595628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 59 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 60/239 9/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 1882396 m, 37161 m/sec, 43315804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 65/239 9/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 2046290 m, 32778 m/sec, 47014684 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 70/239 10/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 2177029 m, 26147 m/sec, 50717715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 74 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 75/239 11/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 2314580 m, 27510 m/sec, 54378567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 79 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 80/239 11/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 2442683 m, 25620 m/sec, 58021207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 84 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 85/239 12/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 2578469 m, 27157 m/sec, 61675903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 89 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 90/239 12/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 2711934 m, 26693 m/sec, 65429244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 94 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 95/239 13/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 2864563 m, 30525 m/sec, 69093190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 99 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 100/239 14/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 3048789 m, 36845 m/sec, 72755705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 104 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 105/239 14/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 3205584 m, 31359 m/sec, 76505826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 109 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 110/239 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 3348655 m, 28614 m/sec, 80243153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 114 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 115/239 16/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 3491690 m, 28607 m/sec, 83934803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 119 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 120/239 16/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 3631096 m, 27881 m/sec, 87553325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 124 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 125/239 17/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 3771895 m, 28159 m/sec, 91197966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 129 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 130/239 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 3909309 m, 27482 m/sec, 94756783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 134 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 135/239 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 4052761 m, 28690 m/sec, 98481532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 139 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 140/239 19/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 4193426 m, 28133 m/sec, 102119154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 144 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 145/239 20/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 4370727 m, 35460 m/sec, 105796501 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 149 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 150/239 20/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 4526148 m, 31084 m/sec, 109481699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 154 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 155/239 21/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 4660437 m, 26857 m/sec, 113178143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 159 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 160/239 21/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 4813404 m, 30593 m/sec, 116813150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 164 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 165/239 22/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 4946718 m, 26662 m/sec, 120456578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 169 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 170/239 23/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 5104236 m, 31503 m/sec, 124090206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 174 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 175/239 23/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 5243362 m, 27825 m/sec, 127688790 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 179 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 180/239 24/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 5382507 m, 27829 m/sec, 131285272 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 184 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 185/239 25/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 5533131 m, 30124 m/sec, 134834826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 189 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 190/239 25/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 5676551 m, 28684 m/sec, 138376127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 194 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 195/239 26/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 5818932 m, 28476 m/sec, 141901040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 199 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 200/239 27/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 5989460 m, 34105 m/sec, 145562687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 204 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 205/239 27/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 6176600 m, 37428 m/sec, 149208882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 209 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 210/239 28/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 6351585 m, 34997 m/sec, 152783216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 214 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 215/239 29/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 6504960 m, 30675 m/sec, 156403622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 219 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 220/239 29/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 6635663 m, 26140 m/sec, 160048217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 224 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 225/239 30/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 6792699 m, 31407 m/sec, 163595010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 229 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 230/239 31/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 6961999 m, 33860 m/sec, 167054311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 234 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 235/239 31/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 7097143 m, 27028 m/sec, 170617224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 239 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 13 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 244 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 PhaseVariation-PT-D05CS100-CTLCardinality-2023-15
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 3356 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 125
[[35mlola[0m][I] fired transitions : 590
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 5/239 1/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 200392 m, -1379350 m/sec, 3442485 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 249 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 10/239 2/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 388911 m, 37703 m/sec, 7166424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 254 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 15/239 3/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 570201 m, 36258 m/sec, 10825321 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 259 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 20/239 4/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 713201 m, 28600 m/sec, 14603458 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 264 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 25/239 4/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 847987 m, 26957 m/sec, 18330295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 269 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 13 CTL EXCL 30/239 5/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 1023758 m, 35154 m/sec, 21939736 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 274 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 13 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-04 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 279 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 PhaseVariation-PT-D05CS100-CTLCardinality-2023-14
[[35mlola[0m][I] time limit : 255 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1781
[[35mlola[0m][I] fired transitions : 2170
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 5/276 1/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 173041 m, 34608 m/sec, 3322665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 284 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 10/276 2/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 356452 m, 36682 m/sec, 6850335 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 289 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 15/276 3/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 532770 m, 35263 m/sec, 10329624 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 294 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 20/276 3/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 673464 m, 28138 m/sec, 13919247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 299 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 25/276 4/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 804369 m, 26181 m/sec, 17488512 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 304 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 30/276 5/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 970874 m, 33301 m/sec, 20930570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 309 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 35/276 5/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 1138897 m, 33604 m/sec, 24308131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 314 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 40/276 6/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 1266975 m, 25615 m/sec, 27838150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 319 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 45/276 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 1393335 m, 25272 m/sec, 31287371 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 324 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 50/276 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 1524972 m, 26327 m/sec, 34855551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 329 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 55/276 8/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 1653744 m, 25754 m/sec, 38337929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 334 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 60/276 8/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 1832337 m, 35718 m/sec, 41881559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 339 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 65/276 9/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 1997594 m, 33051 m/sec, 45396087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 344 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 70/276 10/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 2124468 m, 25374 m/sec, 48941481 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 349 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 75/276 10/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 2256303 m, 26367 m/sec, 52431991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 354 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 80/276 11/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 2383762 m, 25491 m/sec, 55933195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 359 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 85/276 11/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 2511065 m, 25460 m/sec, 59376203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 364 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 90/276 12/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 2644720 m, 26731 m/sec, 62984105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 369 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 95/276 13/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 2772813 m, 25618 m/sec, 66498897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 374 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 100/276 13/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 2957348 m, 36907 m/sec, 69986964 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 379 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 105/276 14/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 3124231 m, 33376 m/sec, 73495956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 384 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 110/276 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 3262366 m, 27627 m/sec, 77081414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 389 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 115/276 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 3403788 m, 28284 m/sec, 80599707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 394 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 120/276 16/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 3537794 m, 26801 m/sec, 84077339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 399 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 125/276 17/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 3677073 m, 27855 m/sec, 87527435 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 404 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 130/276 17/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 3809138 m, 26413 m/sec, 90983331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 409 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 135/276 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 3949767 m, 28125 m/sec, 94434113 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 414 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 140/276 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 4083888 m, 26824 m/sec, 97956954 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 419 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 145/276 19/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 4236544 m, 30531 m/sec, 101417746 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 424 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 150/276 20/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 4392219 m, 31135 m/sec, 104953999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 429 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 155/276 20/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 4542303 m, 30016 m/sec, 108430969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 434 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 160/276 21/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 4683780 m, 28295 m/sec, 111936270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 439 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 165/276 22/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 4823200 m, 27884 m/sec, 115410447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 444 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 170/276 22/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 4952414 m, 25842 m/sec, 118910235 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 449 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 175/276 23/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 5108650 m, 31247 m/sec, 122365304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 454 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 180/276 23/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 5244004 m, 27070 m/sec, 125781118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 459 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 185/276 24/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 5384255 m, 28050 m/sec, 129222497 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 464 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 190/276 25/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 5528246 m, 28798 m/sec, 132584353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 469 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 195/276 25/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 5665339 m, 27418 m/sec, 135957893 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 474 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 200/276 26/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 5804582 m, 27848 m/sec, 139326770 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 479 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 205/276 27/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 5978221 m, 34727 m/sec, 142827715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 484 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 210/276 27/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 6159125 m, 36180 m/sec, 146279548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 489 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 215/276 28/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 6329681 m, 34111 m/sec, 149677686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 494 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 220/276 29/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 6477279 m, 29519 m/sec, 153135748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 499 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 225/276 29/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 6603487 m, 25241 m/sec, 156619990 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 504 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 230/276 30/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 6755936 m, 30489 m/sec, 160000094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 509 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 235/276 31/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 6921004 m, 33013 m/sec, 163293682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 514 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 240/276 31/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 7056224 m, 27044 m/sec, 166699958 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 519 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 245/276 32/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 7179119 m, 24579 m/sec, 170073798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 524 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 250/276 32/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 7307475 m, 25671 m/sec, 173484069 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 529 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 255/276 33/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 7431148 m, 24734 m/sec, 176894526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 534 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 260/276 34/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 7580233 m, 29817 m/sec, 180283563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 539 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 265/276 34/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 7752231 m, 34399 m/sec, 183667759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 544 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 270/276 35/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 7889417 m, 27437 m/sec, 187114994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 549 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 275/276 35/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 8013391 m, 24794 m/sec, 190520860 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 554 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 40 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 559 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 PhaseVariation-PT-D05CS100-CTLCardinality-2023-12
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13
[[35mlola[0m][I] time limit : 3041 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 6603
[[35mlola[0m][I] fired transitions : 19727
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 5/276 1/5 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 168769 m, -1568924 m/sec, 3235187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 564 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 10/276 2/5 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 337846 m, 33815 m/sec, 6430539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 569 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 15/276 3/5 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 513205 m, 35071 m/sec, 9936176 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 574 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 20/276 3/5 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 660475 m, 29454 m/sec, 13528851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 579 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 25/276 4/5 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 790504 m, 26005 m/sec, 17113455 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 584 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 30/276 5/5 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 953331 m, 32565 m/sec, 20580884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 589 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 CTL EXCL 35/276 5/5 PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 1124398 m, 34213 m/sec, 23974724 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 594 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 40 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2023-13 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 599 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 5/300 1/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 188467 m, 37693 m/sec, 3546399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 604 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 10/300 2/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 389331 m, 40172 m/sec, 7291252 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 609 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 15/300 3/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 577743 m, 37682 m/sec, 10982269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 614 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 20/300 4/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 720158 m, 28483 m/sec, 14821382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 619 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 25/300 4/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 873272 m, 30622 m/sec, 18549607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 624 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 30/300 5/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 1062093 m, 37764 m/sec, 22168650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 629 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 35/300 6/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 1217116 m, 31004 m/sec, 25857747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 634 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 40/300 6/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 1353684 m, 27313 m/sec, 29536930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 639 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 45/300 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 1495752 m, 28413 m/sec, 33258941 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 644 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 50/300 8/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 1630846 m, 27018 m/sec, 36897924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 649 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 55/300 8/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 1815540 m, 36938 m/sec, 40625324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 654 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 60/300 9/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 1995745 m, 36041 m/sec, 44353676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 659 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 65/300 10/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 2132572 m, 27365 m/sec, 48104130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 664 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 70/300 10/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 2276708 m, 28827 m/sec, 51810024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 669 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 75/300 11/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 2410879 m, 26834 m/sec, 55496829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 674 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 80/300 12/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 2554413 m, 28706 m/sec, 59185539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 679 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 85/300 12/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 2692067 m, 27530 m/sec, 62971705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 684 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 90/300 13/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 2858919 m, 33370 m/sec, 66674010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 689 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 95/300 14/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 3055761 m, 39368 m/sec, 70325771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 694 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 100/300 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 3212418 m, 31331 m/sec, 74170395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 699 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 105/300 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 3365169 m, 30550 m/sec, 77917240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 704 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 110/300 16/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 3510852 m, 29136 m/sec, 81623957 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 709 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 115/300 16/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 3661051 m, 30039 m/sec, 85271361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 714 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 120/300 17/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 3803117 m, 28413 m/sec, 88920160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 719 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 125/300 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 3954143 m, 30205 m/sec, 92583173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 724 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 130/300 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 4100647 m, 29300 m/sec, 96311706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 729 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 135/300 19/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 4273732 m, 34617 m/sec, 99993866 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 734 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 140/300 20/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 4438678 m, 32989 m/sec, 103737750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 739 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 145/300 21/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 4591870 m, 30638 m/sec, 107449168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 744 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 150/300 21/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 4753355 m, 32297 m/sec, 111141982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 749 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 155/300 22/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 4891894 m, 27707 m/sec, 114823214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 754 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 160/300 23/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 5056206 m, 32862 m/sec, 118497916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 759 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 165/300 23/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 5203183 m, 29395 m/sec, 122159906 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 764 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 170/300 24/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 5349551 m, 29273 m/sec, 125787567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 769 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 175/300 25/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 5508806 m, 31851 m/sec, 129368046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 774 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 180/300 25/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 5657414 m, 29721 m/sec, 132930219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 779 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 185/300 26/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 5806787 m, 29874 m/sec, 136484468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 784 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 190/300 27/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 5997370 m, 38116 m/sec, 140211167 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 789 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 195/300 28/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 6191060 m, 38738 m/sec, 143857151 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 794 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 200/300 28/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 6377446 m, 37277 m/sec, 147420550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 799 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 205/300 29/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 6520138 m, 28538 m/sec, 151124074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 804 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 210/300 30/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 6657102 m, 27392 m/sec, 154752049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 809 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 215/300 30/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 6840637 m, 36707 m/sec, 158288802 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 814 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 220/300 31/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 7006784 m, 33229 m/sec, 161810060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 819 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 225/300 32/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 7137680 m, 26179 m/sec, 165394113 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 824 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 230/300 32/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 7276705 m, 27805 m/sec, 168958051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 829 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 235/300 33/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 7407711 m, 26201 m/sec, 172558035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 834 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 240/300 33/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 7563195 m, 31096 m/sec, 176119000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 839 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 245/300 34/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 7748435 m, 37048 m/sec, 179713811 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 844 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 250/300 35/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 7895427 m, 29398 m/sec, 183349835 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 849 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 255/300 36/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 8029238 m, 26762 m/sec, 186937709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 854 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 260/300 36/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 8166288 m, 27410 m/sec, 190521778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 859 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 265/300 37/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 8297279 m, 26198 m/sec, 194045012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 864 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 270/300 37/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 8436355 m, 27815 m/sec, 197673751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 869 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 275/300 38/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 8569384 m, 26605 m/sec, 201281850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 874 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 280/300 39/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 8746079 m, 35339 m/sec, 204876805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 879 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 285/300 39/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 8931827 m, 37149 m/sec, 208452913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 884 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 290/300 40/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 9077373 m, 29109 m/sec, 212149638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 889 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 295/300 41/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 9227280 m, 29981 m/sec, 215773682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 894 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 300/300 41/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 9366001 m, 27744 m/sec, 219350455 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 899 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 34 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 904 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 PhaseVariation-PT-D05CS100-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 2696 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 179
[[35mlola[0m][I] fired transitions : 811
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 5/299 1/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 187304 m, -1835739 m/sec, 3523457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 909 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 10/299 2/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 388249 m, 40189 m/sec, 7266479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 914 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 15/299 3/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 576484 m, 37647 m/sec, 10952256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 919 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 20/299 4/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 718896 m, 28482 m/sec, 14784874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 924 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 25/299 4/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 871229 m, 30466 m/sec, 18501653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 929 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 34 CTL EXCL 30/299 5/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 1059279 m, 37610 m/sec, 22114197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 934 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 34 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 939 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 PhaseVariation-PT-D05CS100-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 332 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 13356
[[35mlola[0m][I] fired transitions : 218346
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 380 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 5/380 1/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 164315 m, 32863 m/sec, 3219587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 944 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 10/380 2/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 349882 m, 37113 m/sec, 6825593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 949 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 15/380 3/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 524687 m, 34961 m/sec, 10395897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 954 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 20/380 3/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 659810 m, 27024 m/sec, 14103040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 959 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 25/380 4/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 810378 m, 30113 m/sec, 17689331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 964 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 30/380 5/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 982397 m, 34403 m/sec, 21174423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 969 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 35/380 5/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 1122303 m, 27981 m/sec, 24767330 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 974 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 40/380 6/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 1253331 m, 26205 m/sec, 28302297 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 979 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 45/380 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 1389835 m, 27300 m/sec, 31929703 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 984 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 50/380 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 1527298 m, 27492 m/sec, 35479539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 989 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 55/380 8/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 1707398 m, 36020 m/sec, 39092814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 994 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 60/380 9/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 1857848 m, 30090 m/sec, 42713915 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 999 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 65/380 9/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 1988358 m, 26102 m/sec, 46308862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1004 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 70/380 10/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 2116843 m, 25697 m/sec, 49723923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1009 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 75/380 10/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 2245692 m, 25769 m/sec, 53254522 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1014 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 80/380 11/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 2382246 m, 27310 m/sec, 56917969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1019 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 85/380 11/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 2516940 m, 26938 m/sec, 60515072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1024 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 90/380 12/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 2703907 m, 37393 m/sec, 64081204 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1029 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 95/380 13/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 2864241 m, 32066 m/sec, 67709734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1034 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 100/380 14/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 3005295 m, 28210 m/sec, 71353511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1039 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 105/380 14/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 3149214 m, 28783 m/sec, 74949311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1044 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 110/380 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 3288962 m, 27949 m/sec, 78468599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1049 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 115/380 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 3426488 m, 27505 m/sec, 82018784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1054 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 120/380 16/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 3569334 m, 28569 m/sec, 85555014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1059 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 125/380 17/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 3707808 m, 27694 m/sec, 89176504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1064 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 130/380 17/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 3869648 m, 32368 m/sec, 92740014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1069 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 135/380 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 4025558 m, 31182 m/sec, 96365439 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1074 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 140/380 19/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 4167529 m, 28394 m/sec, 99967358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1079 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 145/380 19/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 4319195 m, 30333 m/sec, 103533809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1084 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 150/380 20/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 4451818 m, 26524 m/sec, 107104150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1089 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 155/380 21/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 4607232 m, 31082 m/sec, 110656308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1094 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 160/380 21/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 4746284 m, 27810 m/sec, 114175901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1099 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 165/380 22/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 4891586 m, 29060 m/sec, 117698954 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1104 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 170/380 22/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 5032028 m, 28088 m/sec, 121164104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1109 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 175/380 23/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 5171957 m, 27985 m/sec, 124611749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1114 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 180/380 24/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 5334835 m, 32575 m/sec, 128092882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1119 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 185/380 25/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 5511375 m, 35308 m/sec, 131675615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1124 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 190/380 25/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 5690150 m, 35755 m/sec, 135161115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1129 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 195/380 26/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 5846880 m, 31346 m/sec, 138665102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1134 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 200/380 27/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 5976767 m, 25977 m/sec, 142227734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1139 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 205/380 27/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 6133049 m, 31256 m/sec, 145675225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1144 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 210/380 28/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 6299110 m, 33212 m/sec, 149042751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1149 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 215/380 29/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 6428476 m, 25873 m/sec, 152547970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1154 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 220/380 29/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 6557556 m, 25816 m/sec, 155986453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1159 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 225/380 30/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 6686072 m, 25703 m/sec, 159503358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1164 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 230/380 30/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 6825620 m, 27909 m/sec, 162956351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1169 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 235/380 31/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 6998678 m, 34611 m/sec, 166432484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1174 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 240/380 32/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 7135883 m, 27441 m/sec, 169769933 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1179 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 245/380 32/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 7262195 m, 25262 m/sec, 173254572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1184 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 250/380 33/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 7393006 m, 26162 m/sec, 176722960 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1189 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 255/380 33/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 7517749 m, 24948 m/sec, 180146833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1194 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 260/380 34/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 7650079 m, 26466 m/sec, 183668596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1199 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 265/380 34/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 7777746 m, 25533 m/sec, 187162073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1204 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 270/380 35/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 7954839 m, 35418 m/sec, 190628506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1209 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 275/380 36/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 8116559 m, 32344 m/sec, 194127837 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1214 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 280/380 36/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 8254748 m, 27637 m/sec, 197689396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1219 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 285/380 37/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 8395026 m, 28055 m/sec, 201188642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1224 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 290/380 38/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 8527169 m, 26428 m/sec, 204617688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1229 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 295/380 38/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 8663693 m, 27304 m/sec, 208062840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1234 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 300/380 39/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 8796206 m, 26502 m/sec, 211432500 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1239 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 305/380 39/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 8936414 m, 28041 m/sec, 214944683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1244 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 310/380 40/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 9075601 m, 27837 m/sec, 218381584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1249 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 315/380 41/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 9235592 m, 31998 m/sec, 221874431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1254 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 320/380 41/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 9383274 m, 29536 m/sec, 225340937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1259 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 325/380 42/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 9522990 m, 27943 m/sec, 228805332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1264 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 330/380 43/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 9658574 m, 27116 m/sec, 232243463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1269 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 335/380 43/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 9794434 m, 27172 m/sec, 235686528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1274 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 340/380 44/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 9940676 m, 29248 m/sec, 239108601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1279 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 345/380 44/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 10074636 m, 26792 m/sec, 242490551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1284 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 350/380 45/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 10215946 m, 28262 m/sec, 245871877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1289 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 355/380 46/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 10346603 m, 26131 m/sec, 249198672 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1294 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 360/380 46/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 10488850 m, 28449 m/sec, 252522505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1299 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 365/380 47/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 10624790 m, 27188 m/sec, 256049005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1304 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 370/380 47/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 10748532 m, 24748 m/sec, 259718268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1309 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 375/380 48/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 10874435 m, 25180 m/sec, 263326065 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1314 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 CTL EXCL 380/380 48/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 10994300 m, 23973 m/sec, 266892349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1319 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 25 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1324 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06
[[35mlola[0m][I] time limit : 379 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 2276 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 5/379 1/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 190285 m, 38057 m/sec, 3772932 t fired, .
[[35mlola[0m][.] 25 CTL EXCL 5/2276 1/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 185574 m, -2161745 m/sec, 3639929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1329 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 10/379 2/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 381832 m, 38309 m/sec, 7510095 t fired, .
[[35mlola[0m][.] 25 CTL EXCL 10/325 2/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 359171 m, 34719 m/sec, 7038034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1334 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 15/379 3/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 561324 m, 35898 m/sec, 11178116 t fired, .
[[35mlola[0m][.] 25 CTL EXCL 15/325 3/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 530057 m, 34177 m/sec, 10536890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1339 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 20/379 4/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 700738 m, 27882 m/sec, 14987708 t fired, .
[[35mlola[0m][.] 25 CTL EXCL 20/325 3/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 661492 m, 26287 m/sec, 14150781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1344 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 25/379 4/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 824042 m, 24660 m/sec, 18433431 t fired, .
[[35mlola[0m][.] 25 CTL EXCL 25/325 4/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 808904 m, 29482 m/sec, 17657436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1349 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 30/379 5/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 1003050 m, 35801 m/sec, 22046529 t fired, .
[[35mlola[0m][.] 25 CTL EXCL 30/325 5/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 970005 m, 32220 m/sec, 20934182 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1354 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 35/379 6/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 1167414 m, 32872 m/sec, 25649542 t fired, .
[[35mlola[0m][.] 25 CTL EXCL 35/325 5/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 1111460 m, 28291 m/sec, 24442497 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1359 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 25 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-08 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 40/379 6/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 1296952 m, 25907 m/sec, 29337882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1364 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 45/379 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 1433684 m, 27346 m/sec, 33015631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1369 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 50/379 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 1566223 m, 26507 m/sec, 36744347 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1374 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 55/379 8/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 1718223 m, 30400 m/sec, 40438527 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1379 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 60/379 9/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 1901720 m, 36699 m/sec, 44204410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1384 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 65/379 9/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 2052651 m, 30186 m/sec, 47975357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1389 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 70/379 10/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 2186015 m, 26672 m/sec, 51698577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1394 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 75/379 11/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 2323041 m, 27405 m/sec, 55403953 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1399 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 80/379 11/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 2453235 m, 26038 m/sec, 59064020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1404 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 85/379 12/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 2592179 m, 27788 m/sec, 62804636 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1409 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 90/379 12/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 2725539 m, 26672 m/sec, 66563810 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1414 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 95/379 13/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 2896580 m, 34208 m/sec, 70282409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1419 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 100/379 14/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 3083171 m, 37318 m/sec, 73971227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1424 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 105/379 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 3227979 m, 28961 m/sec, 77808112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1429 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 110/379 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 3375231 m, 29450 m/sec, 81563774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1434 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 115/379 16/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 3515215 m, 27996 m/sec, 85257756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1439 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 120/379 16/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 3660081 m, 28973 m/sec, 88909122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1444 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 125/379 17/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 3797110 m, 27405 m/sec, 92562993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1449 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 130/379 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 3942970 m, 29172 m/sec, 96215393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1454 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 135/379 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 4082627 m, 27931 m/sec, 99961917 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1459 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 140/379 19/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 4241249 m, 31724 m/sec, 103635301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1464 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 145/379 20/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 4400985 m, 31947 m/sec, 107401256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1469 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 150/379 20/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 4557044 m, 31211 m/sec, 111100744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1474 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 155/379 21/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 4710406 m, 30672 m/sec, 114818969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1479 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 160/379 22/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 4847954 m, 27509 m/sec, 118503227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1484 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 165/379 22/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 4991205 m, 28650 m/sec, 122195552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1489 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 170/379 23/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 5145786 m, 30916 m/sec, 125863232 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1494 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 175/379 24/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 5285458 m, 27934 m/sec, 129476680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1499 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 180/379 24/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 5436268 m, 30162 m/sec, 133119218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1504 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 185/379 25/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 5579622 m, 28670 m/sec, 136681077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1509 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 190/379 25/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 5725710 m, 29217 m/sec, 140248630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1514 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 195/379 26/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 5882915 m, 31441 m/sec, 143859484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1519 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 200/379 27/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 6066285 m, 36674 m/sec, 147603259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1524 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 205/379 28/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 6249290 m, 36601 m/sec, 151241649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1529 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 210/379 29/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 6421934 m, 34528 m/sec, 154838066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1534 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 215/379 29/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 6554108 m, 26434 m/sec, 158542167 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1539 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 220/379 30/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 6694571 m, 28092 m/sec, 162136453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1544 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 225/379 30/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 6866172 m, 34320 m/sec, 165671686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1549 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 230/379 31/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 7020195 m, 30804 m/sec, 169227043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1554 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 235/379 32/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 7147072 m, 25375 m/sec, 172792646 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1559 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 240/379 32/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 7280698 m, 26725 m/sec, 176352493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1564 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 245/379 33/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 7407237 m, 25307 m/sec, 179951695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1569 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 250/379 33/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 7556140 m, 29780 m/sec, 183519285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1574 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 255/379 34/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 7732622 m, 35296 m/sec, 187142207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1579 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 260/379 35/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 7879873 m, 29450 m/sec, 190769623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1584 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 265/379 35/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 8007950 m, 25615 m/sec, 194367441 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1589 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 270/379 36/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 8139529 m, 26315 m/sec, 197946152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1594 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 275/379 37/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 8265828 m, 25259 m/sec, 201484898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1599 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 280/379 37/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 8399045 m, 26643 m/sec, 205066798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1604 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 285/379 38/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 8527379 m, 25666 m/sec, 208702088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1609 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 290/379 38/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 8680959 m, 30716 m/sec, 212280427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1614 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 295/379 39/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 8862751 m, 36358 m/sec, 215857326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1619 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 300/379 40/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 9012857 m, 30021 m/sec, 219539981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1624 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 305/379 40/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 9153397 m, 28108 m/sec, 223192328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1629 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 310/379 41/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 9292697 m, 27860 m/sec, 226791880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1634 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 315/379 42/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 9428345 m, 27129 m/sec, 230310912 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1639 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 320/379 42/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 9566166 m, 27564 m/sec, 233861475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1644 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 325/379 43/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 9699483 m, 26663 m/sec, 237345227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1649 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 330/379 43/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 9840544 m, 28212 m/sec, 240955487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1654 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 335/379 44/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 9976350 m, 27161 m/sec, 244511564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1659 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 340/379 45/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 10148051 m, 34340 m/sec, 248096452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1664 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 345/379 45/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 10299101 m, 30210 m/sec, 251723993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1669 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 350/379 46/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 10435599 m, 27299 m/sec, 255324266 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1674 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 355/379 47/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 10586924 m, 30265 m/sec, 258885554 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1679 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 360/379 47/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 10714686 m, 25552 m/sec, 262426321 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1684 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 365/379 48/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 10864142 m, 29891 m/sec, 265969419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1689 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 370/379 48/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 11004211 m, 28013 m/sec, 269511087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1694 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 375/379 49/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 11139708 m, 27099 m/sec, 272992309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1699 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 19 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1704 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 379 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06
[[35mlola[0m][I] time limit : 1896 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 5/379 1/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 196820 m, 39364 m/sec, 3832764 t fired, .
[[35mlola[0m][.] 19 CTL EXCL 5/1896 1/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 190467 m, -2189848 m/sec, 3777151 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1709 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 10/379 2/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 374023 m, 35440 m/sec, 7626091 t fired, .
[[35mlola[0m][.] 19 CTL EXCL 10/316 2/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 382142 m, 38335 m/sec, 7517855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1714 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 15/379 3/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 552056 m, 35606 m/sec, 11447914 t fired, .
[[35mlola[0m][.] 19 CTL EXCL 15/316 3/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 561249 m, 35821 m/sec, 11176426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1719 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 20/379 4/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 710625 m, 31713 m/sec, 15245300 t fired, .
[[35mlola[0m][.] 19 CTL EXCL 20/316 4/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 699905 m, 27731 m/sec, 14967658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1724 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 25/379 4/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 895552 m, 36985 m/sec, 18978863 t fired, .
[[35mlola[0m][.] 19 CTL EXCL 25/316 4/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 822134 m, 24445 m/sec, 18377516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1729 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 30/379 5/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 1062097 m, 33309 m/sec, 22668187 t fired, .
[[35mlola[0m][.] 19 CTL EXCL 30/316 5/5 PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 1001929 m, 35959 m/sec, 22024740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1734 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 19 (type EXCL) for PhaseVariation-PT-D05CS100-CTLCardinality-2024-06 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 35/379 6/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 1232413 m, 34063 m/sec, 26163178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1739 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 40/379 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 1399447 m, 33406 m/sec, 29777863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1744 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 45/379 7/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 1581204 m, 36351 m/sec, 33430875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1749 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 50/379 8/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 1766294 m, 37018 m/sec, 37179177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1754 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 55/379 9/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 1935353 m, 33811 m/sec, 40906642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1759 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 60/379 10/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 2107374 m, 34404 m/sec, 44599189 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1764 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 65/379 10/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 2264579 m, 31441 m/sec, 48287172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1769 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 70/379 11/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 2444332 m, 35950 m/sec, 51928483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1774 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 75/379 12/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 2608118 m, 32757 m/sec, 55554251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1779 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 80/379 13/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 2786380 m, 35652 m/sec, 59204417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1784 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 85/379 13/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 2955198 m, 33763 m/sec, 62784223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1789 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 90/379 14/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 3118089 m, 32578 m/sec, 66411915 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1794 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 95/379 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 3262562 m, 28894 m/sec, 70172980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1799 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 100/379 15/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 3402687 m, 28025 m/sec, 73875045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1804 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 105/379 16/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 3537771 m, 27016 m/sec, 77590934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1809 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 110/379 16/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 3667806 m, 26007 m/sec, 81255049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1814 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 115/379 17/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 3794131 m, 25265 m/sec, 84913497 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1819 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 120/379 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 3937441 m, 28662 m/sec, 88554835 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1824 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 125/379 18/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 4066726 m, 25857 m/sec, 92140896 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1829 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 130/379 19/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 4203657 m, 27386 m/sec, 95796205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1834 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 135/379 19/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 4339125 m, 27093 m/sec, 99389286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1839 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 140/379 20/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 4472467 m, 26668 m/sec, 102948842 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1844 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 145/379 20/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 4612311 m, 27968 m/sec, 106460909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1849 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-05: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-07: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS100-CTLCardinality-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 150/379 21/2000 PhaseVariation-PT-D05CS100-CTLCardinality-2024-03 4794871 m, 36512 m/sec, 110138026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1854 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-01: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS100-CTLCardinality-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS100-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PhaseVariation-PT-D05CS100"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PhaseVariation-PT-D05CS100, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408600321"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PhaseVariation-PT-D05CS100.tgz
mv PhaseVariation-PT-D05CS100 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;