About the Execution of LoLA for PhaseVariation-PT-D05CS010
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 10368.596 | 3600000.00 | 3648712.00 | 12753.10 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408600313.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PhaseVariation-PT-D05CS010, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408600313
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 6.5K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 55K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 72K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.3K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K May 19 07:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 18:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 11 20:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 124K Apr 11 20:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 15K Apr 11 20:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Apr 11 20:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 9 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 633K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-00
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-01
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-02
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-03
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-04
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-05
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-06
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-07
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-08
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-09
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-10
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2024-11
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2023-12
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2023-13
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2023-14
FORMULA_NAME PhaseVariation-PT-D05CS010-CTLCardinality-2023-15
=== Now, execution of the tool begins
BK_START 1717166692378
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] Rule S: 52 transitions removed,2 places removed
[[35mlola[0m][I] LAUNCH task # 31 (type CNST) for 30 PhaseVariation-PT-D05CS010-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 31 (type CNST) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 4/211 2/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 267942 m, 53588 m/sec, 4316441 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 9/211 3/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 515919 m, 49595 m/sec, 8782277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 14/211 4/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 753099 m, 47436 m/sec, 13262634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 19/211 5/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 977284 m, 44837 m/sec, 17745796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 24/211 6/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 1223615 m, 49266 m/sec, 22320809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 29/211 7/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 1454782 m, 46233 m/sec, 26573524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 34/211 8/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 1669895 m, 43022 m/sec, 30684719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 39/211 8/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 1880029 m, 42026 m/sec, 34808330 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 44/211 9/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 2087158 m, 41425 m/sec, 38945771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 49/211 10/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 2281181 m, 38804 m/sec, 43023887 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 54/211 11/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 2476583 m, 39080 m/sec, 47074351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 59/211 12/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 2675002 m, 39683 m/sec, 51203080 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 64/211 13/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 2860371 m, 37073 m/sec, 55216503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 69/211 13/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 3035784 m, 35082 m/sec, 59347984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 74/211 14/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 3245682 m, 41979 m/sec, 63510717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 79/211 15/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 3472369 m, 45337 m/sec, 67626808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 84/211 16/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 3684232 m, 42372 m/sec, 71693611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 89/211 17/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 3891665 m, 41486 m/sec, 75766455 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 94/211 18/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 4104029 m, 42472 m/sec, 79951521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 99/211 19/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 4300199 m, 39234 m/sec, 84119105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 104/211 19/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 4506340 m, 41228 m/sec, 88252270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 109/211 20/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 4700660 m, 38864 m/sec, 92405778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 114/211 21/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 4893102 m, 38488 m/sec, 96579634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 119/211 22/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 5076449 m, 36669 m/sec, 100633664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 124/211 23/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 5256264 m, 35963 m/sec, 104541788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 129/211 23/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 5458333 m, 40413 m/sec, 108292397 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 134/211 24/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 5640676 m, 36468 m/sec, 111963991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 139/211 25/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 5837683 m, 39401 m/sec, 115665509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 144/211 26/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 6018222 m, 36107 m/sec, 119309600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 149/211 27/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 6194822 m, 35320 m/sec, 122917044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 154/211 27/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 6374484 m, 35932 m/sec, 126521307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 159/211 28/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 6535448 m, 32192 m/sec, 130093232 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 164/211 29/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 6714337 m, 35777 m/sec, 133816090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 169/211 29/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 6891692 m, 35471 m/sec, 137518183 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 174/211 30/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 7077245 m, 37110 m/sec, 141318499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 179/211 31/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 7251521 m, 34855 m/sec, 145061147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 184/211 32/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 7413312 m, 32358 m/sec, 148805951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 189/211 32/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 7579849 m, 33307 m/sec, 152548013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 194/211 33/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 7766006 m, 37231 m/sec, 156474188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 199/211 34/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 7939911 m, 34781 m/sec, 160370325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 204/211 35/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 8105169 m, 33051 m/sec, 164272346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 209/211 35/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 8294328 m, 37831 m/sec, 168216650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 3384 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 6/3384 2/5 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 263159 m, -1606233 m/sec, 4238720 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 6/211 2/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 278223 m, 55644 m/sec, 4228916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 222 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 11/3384 3/5 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 495992 m, 46566 m/sec, 8393245 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 11/199 3/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 524563 m, 49268 m/sec, 8409124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 227 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 16/3384 4/5 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 715728 m, 43947 m/sec, 12544773 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 16/199 4/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 754773 m, 46042 m/sec, 12538545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 232 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 21/3384 4/5 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 927919 m, 42438 m/sec, 16709126 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 21/199 5/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 973696 m, 43784 m/sec, 16690057 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 237 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 26/3384 5/5 PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 1145464 m, 43509 m/sec, 20911181 t fired, .
[[35mlola[0m][.] 54 CTL EXCL 26/199 6/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 1212831 m, 47827 m/sec, 20901453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 242 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 7 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 31/199 7/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 1451629 m, 47759 m/sec, 25068169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 247 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 36/211 8/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 1669421 m, 43558 m/sec, 29006168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 252 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 41/211 8/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 1880895 m, 42294 m/sec, 32946056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 257 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 46/211 9/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 2089140 m, 41649 m/sec, 36899305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 262 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 51/211 10/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 2284971 m, 39166 m/sec, 40817902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 267 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 56/211 11/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 2480418 m, 39089 m/sec, 44679539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 272 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 61/211 12/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 2679746 m, 39865 m/sec, 48638628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 277 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 66/211 13/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 2865346 m, 37120 m/sec, 52460917 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 282 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 71/211 13/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 3039731 m, 34877 m/sec, 56409588 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 287 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 76/211 14/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 3251498 m, 42353 m/sec, 60362448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 81/211 15/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 3477859 m, 45272 m/sec, 64249950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 86/211 16/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 3690195 m, 42467 m/sec, 68104385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 91/211 17/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 3902593 m, 42479 m/sec, 72085764 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 96/211 18/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 4123108 m, 44103 m/sec, 76218349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 101/211 19/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 4327457 m, 40869 m/sec, 80314373 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 106/211 20/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 4535803 m, 41669 m/sec, 84391503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 111/211 20/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 4737433 m, 40326 m/sec, 88500504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 116/211 21/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 4938163 m, 40146 m/sec, 92642826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 121/211 22/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 5123973 m, 37162 m/sec, 96673117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 126/211 23/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 5335941 m, 42393 m/sec, 100673735 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 131/211 24/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 5552966 m, 43405 m/sec, 104568644 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 136/211 25/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 5755418 m, 40490 m/sec, 108360784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 141/211 26/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 5957514 m, 40419 m/sec, 112193780 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 146/211 26/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 6158131 m, 40123 m/sec, 115981147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 151/211 27/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 6354628 m, 39299 m/sec, 119790692 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 156/211 28/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 6532990 m, 35672 m/sec, 123506654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 161/211 29/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 6731180 m, 39638 m/sec, 127395362 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 166/211 30/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 6923624 m, 38488 m/sec, 131241007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 171/211 30/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 7121553 m, 39585 m/sec, 135178211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 176/211 31/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 7306079 m, 36905 m/sec, 138999683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 181/211 32/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 7476087 m, 34001 m/sec, 142881257 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 186/211 33/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 7666938 m, 38170 m/sec, 146694414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 191/211 33/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 7852221 m, 37056 m/sec, 150464467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 196/211 34/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 8023869 m, 34329 m/sec, 154242704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 201/211 35/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 8200894 m, 35405 m/sec, 158042005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 206/211 36/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 8387386 m, 37298 m/sec, 161928590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 211/211 36/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 8563632 m, 35249 m/sec, 165819641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 54 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 PhaseVariation-PT-D05CS010-CTLCardinality-2023-14
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15
[[35mlola[0m][I] time limit : 3168 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 26
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 5/211 2/5 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 282635 m, -1656199 m/sec, 4313208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 10/211 3/5 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 529917 m, 49456 m/sec, 8499464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 15/211 4/5 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 760330 m, 46082 m/sec, 12643241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 20/211 5/5 PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 979004 m, 43734 m/sec, 16804398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 54 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2023-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 40 PhaseVariation-PT-D05CS010-CTLCardinality-2023-12
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2023-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 33 PhaseVariation-PT-D05CS010-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 241 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 76
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 PhaseVariation-PT-D05CS010-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 285 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 PhaseVariation-PT-D05CS010-CTLCardinality-2024-06
[[35mlola[0m][I] time limit : 314 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 118134
[[35mlola[0m][I] fired transitions : 1751952
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 PhaseVariation-PT-D05CS010-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 349 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 101
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 392 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 3/392 1/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 168564 m, 33712 m/sec, 2514149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 8/392 2/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 415419 m, 49371 m/sec, 6566472 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 467 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 13/392 3/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 647679 m, 46452 m/sec, 10655988 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 472 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 18/392 4/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 868276 m, 44119 m/sec, 14685665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 477 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 23/392 5/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 1079479 m, 42240 m/sec, 18767894 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 482 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 28/392 6/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 1322163 m, 48536 m/sec, 22847162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 487 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 33/392 7/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 1545149 m, 44597 m/sec, 26766082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 38/392 8/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 1747556 m, 40481 m/sec, 30707134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 43/392 9/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 1971896 m, 44868 m/sec, 34658460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 48/392 10/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 2168180 m, 39256 m/sec, 38637591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 53/392 10/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 2372172 m, 40798 m/sec, 42492478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 58/392 11/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 2568783 m, 39322 m/sec, 46426979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 63/392 12/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 2762659 m, 38775 m/sec, 50376129 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 68/392 13/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 2941925 m, 35853 m/sec, 54240756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 73/392 14/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 3113756 m, 34366 m/sec, 58232619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 78/392 15/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 3349539 m, 47156 m/sec, 62166154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 83/392 16/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 3575284 m, 45149 m/sec, 66019808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 88/392 16/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 3779685 m, 40880 m/sec, 69834970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 93/392 17/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 3991345 m, 42332 m/sec, 73752422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 98/392 18/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 4194138 m, 40558 m/sec, 77650663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 103/392 19/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 4389869 m, 39146 m/sec, 81580567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 108/392 20/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 4585047 m, 39035 m/sec, 85516504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 113/392 21/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 4779865 m, 38963 m/sec, 89539951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 118/392 21/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 4978511 m, 39729 m/sec, 93486900 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 123/392 22/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 5151199 m, 34537 m/sec, 97376612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 582 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 128/392 23/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 5365563 m, 42872 m/sec, 101209246 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 587 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 133/392 24/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 5566447 m, 40176 m/sec, 104879178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 592 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 138/392 25/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 5758879 m, 38486 m/sec, 108480575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 597 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 143/392 26/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 5953171 m, 38858 m/sec, 112142301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 602 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 148/392 26/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 6146636 m, 38693 m/sec, 115787722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 607 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 153/392 27/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 6331629 m, 36998 m/sec, 119392653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 612 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 158/392 28/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 6505256 m, 34725 m/sec, 122949784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 617 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 163/392 29/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 6685248 m, 35998 m/sec, 126599158 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 622 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 168/392 29/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 6875994 m, 38149 m/sec, 130323441 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 627 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 173/392 30/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 7070809 m, 38963 m/sec, 134148647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 632 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 178/392 31/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 7251440 m, 36126 m/sec, 137855165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 637 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 183/392 32/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 7419231 m, 33558 m/sec, 141577593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 642 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 188/392 32/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 7595385 m, 35230 m/sec, 145306464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 647 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 193/392 33/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 7782073 m, 37337 m/sec, 149073064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 652 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 198/392 34/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 7957093 m, 35004 m/sec, 152831333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 657 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 203/392 35/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 8120056 m, 32592 m/sec, 156571480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 662 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 208/392 35/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 8310657 m, 38120 m/sec, 160326332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 667 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 213/392 36/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 8486350 m, 35138 m/sec, 164192171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 672 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 218/392 37/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 8659278 m, 34585 m/sec, 167885011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 677 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 223/392 38/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 8824482 m, 33040 m/sec, 171510561 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 682 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 228/392 38/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 8981512 m, 31406 m/sec, 175304210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 687 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 233/392 39/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 9143150 m, 32327 m/sec, 179045532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 692 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 238/392 40/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 9295522 m, 30474 m/sec, 182873924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 697 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 243/392 41/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 9526163 m, 46128 m/sec, 186876101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 702 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 248/392 42/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 9764332 m, 47633 m/sec, 190845147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 707 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 253/392 42/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 9974775 m, 42088 m/sec, 194696295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 712 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 258/392 43/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 10200003 m, 45045 m/sec, 198755127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 717 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 263/392 44/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 10413680 m, 42735 m/sec, 202813772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 722 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 268/392 45/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 10622389 m, 41741 m/sec, 206746584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 727 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 273/392 46/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 10825811 m, 40684 m/sec, 210671550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 732 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 278/392 47/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 11014384 m, 37714 m/sec, 214519798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 737 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 283/392 48/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 11202185 m, 37560 m/sec, 218298818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 742 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 288/392 48/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 11370981 m, 33759 m/sec, 222127000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 747 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 293/392 49/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 11605831 m, 46970 m/sec, 226134196 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 752 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 298/392 50/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 11815214 m, 41876 m/sec, 230128595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 757 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 303/392 51/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 12035814 m, 44120 m/sec, 233986384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 762 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 308/392 52/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 12238656 m, 40568 m/sec, 237820857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 313/392 53/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 12430493 m, 38367 m/sec, 241588803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 772 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 318/392 54/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 12613124 m, 36526 m/sec, 245273521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 323/392 54/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 12793095 m, 35994 m/sec, 248990058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 782 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 328/392 55/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 12995286 m, 40438 m/sec, 252847999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 787 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 333/392 56/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 13193415 m, 39625 m/sec, 256655396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 338/392 57/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 13381849 m, 37686 m/sec, 260429777 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 797 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 343/392 58/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 13560836 m, 35797 m/sec, 264270483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 802 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 348/392 58/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 13739039 m, 35640 m/sec, 267974347 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 807 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 353/392 59/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 13929437 m, 38079 m/sec, 271683256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 812 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 358/392 60/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 14117156 m, 37543 m/sec, 275385470 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 817 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 363/392 61/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 14291146 m, 34798 m/sec, 279148452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 822 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 368/392 61/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 14470724 m, 35915 m/sec, 282806975 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 827 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 373/392 62/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 14635483 m, 32951 m/sec, 286552338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 832 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 378/392 63/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 14809006 m, 34704 m/sec, 290152175 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 837 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 383/392 63/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 14974816 m, 33162 m/sec, 293741528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 842 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 388/392 64/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 15141284 m, 33293 m/sec, 297397742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 847 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 10 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 852 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 PhaseVariation-PT-D05CS010-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 392 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 2748 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 29
[[35mlola[0m][I] fired transitions : 40
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 5/392 2/5 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 268171 m, -2974622 m/sec, 4099440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 857 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 10/392 3/5 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 508029 m, 47971 m/sec, 8162147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 862 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 15/392 4/5 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 730280 m, 44450 m/sec, 12176731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 867 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 20/392 4/5 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 946670 m, 43278 m/sec, 16199455 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 872 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 25/392 5/5 PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 1171246 m, 44915 m/sec, 20261022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 877 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 10 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-03 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 882 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 453 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 5/453 1/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 161815 m, 32363 m/sec, 3412325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 887 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 10/453 2/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 304684 m, 28573 m/sec, 6578878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 892 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 15/453 2/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 443185 m, 27700 m/sec, 9922111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 897 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 20/453 3/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 572980 m, 25959 m/sec, 13400826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 902 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 25/453 3/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 700217 m, 25447 m/sec, 16636949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 907 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 30/453 4/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 837837 m, 27524 m/sec, 20081087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 912 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 35/453 4/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 926327 m, 17698 m/sec, 23142371 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 917 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 40/453 5/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 1091561 m, 33046 m/sec, 26800736 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 922 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 45/453 6/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 1226192 m, 26926 m/sec, 30125645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 927 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 50/453 6/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 1360328 m, 26827 m/sec, 33473122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 932 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 55/453 7/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 1496497 m, 27233 m/sec, 36929589 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 937 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 60/453 7/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 1605271 m, 21754 m/sec, 39849753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 942 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 65/453 8/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 1749520 m, 28849 m/sec, 43551878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 947 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 70/453 8/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 1875550 m, 25206 m/sec, 46770890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 952 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 75/453 9/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 1995901 m, 24070 m/sec, 49182552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 957 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 80/453 9/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 2083626 m, 17545 m/sec, 53009923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 962 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 85/453 10/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 2232209 m, 29716 m/sec, 56344838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 967 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 90/453 10/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 2301223 m, 13802 m/sec, 59146589 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 972 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 95/453 11/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 2451132 m, 29981 m/sec, 62804607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 977 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 100/453 11/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 2580381 m, 25849 m/sec, 65543308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 982 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 105/453 12/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 2683310 m, 20585 m/sec, 67764215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 987 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 110/453 12/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 2705574 m, 4452 m/sec, 71344837 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 992 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 115/453 12/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 2823133 m, 23511 m/sec, 75098148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 997 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 120/453 13/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 2980805 m, 31534 m/sec, 78877474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1002 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 125/453 14/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 3133014 m, 30441 m/sec, 82717471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1007 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 130/453 14/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 3281697 m, 29736 m/sec, 86119255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1012 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 135/453 15/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 3415064 m, 26673 m/sec, 89507782 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1017 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 140/453 15/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 3555327 m, 28052 m/sec, 92817233 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1022 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 145/453 16/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 3683005 m, 25535 m/sec, 96224813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1027 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 150/453 16/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 3796660 m, 22731 m/sec, 99460533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1032 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 155/453 17/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 3925219 m, 25711 m/sec, 102859303 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1037 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 160/453 18/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 4067798 m, 28515 m/sec, 106486656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1042 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 165/453 18/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 4161522 m, 18744 m/sec, 109686891 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1047 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 170/453 19/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 4307108 m, 29117 m/sec, 113282824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1052 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 175/453 19/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 4441891 m, 26956 m/sec, 116402130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1057 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 180/453 20/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 4568025 m, 25226 m/sec, 120492904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1062 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 185/453 20/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 4656467 m, 17688 m/sec, 123679717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1067 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 190/453 21/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 4814785 m, 31663 m/sec, 127218044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1072 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 195/453 21/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 4913634 m, 19769 m/sec, 129697056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1077 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 200/453 21/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 4989623 m, 15197 m/sec, 133869691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1082 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 205/453 22/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 5150708 m, 32217 m/sec, 137846775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1087 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 210/453 23/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 5294012 m, 28660 m/sec, 141287970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1092 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 215/453 23/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 5433155 m, 27828 m/sec, 144824463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1097 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 220/453 24/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 5562082 m, 25785 m/sec, 147818762 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1102 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 225/453 24/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 5687343 m, 25052 m/sec, 151336798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1107 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 230/453 25/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 5819932 m, 26517 m/sec, 154455869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1112 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 235/453 25/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 5934288 m, 22871 m/sec, 158185674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1117 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 240/453 26/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 6040507 m, 21243 m/sec, 161203060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1122 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 245/453 27/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 6190127 m, 29924 m/sec, 164861494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1127 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 250/453 27/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 6301445 m, 22263 m/sec, 167067800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1132 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 255/453 27/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 6335172 m, 6745 m/sec, 170600998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1137 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 260/453 28/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 6499012 m, 32768 m/sec, 174289076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1142 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 265/453 28/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 6644277 m, 29053 m/sec, 177564229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1147 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 270/453 29/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 6713318 m, 13808 m/sec, 180819097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1152 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 275/453 29/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 6889221 m, 35180 m/sec, 184657006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1157 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 280/453 30/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 7010994 m, 24354 m/sec, 187129493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1162 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 285/453 30/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 7105818 m, 18964 m/sec, 189630434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1167 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 290/453 30/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 7126841 m, 4204 m/sec, 193825849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1172 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 295/453 31/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 7295045 m, 33640 m/sec, 197642922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1177 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 300/453 32/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 7451488 m, 31288 m/sec, 201486766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1182 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 305/453 32/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 7583912 m, 26484 m/sec, 204433238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1187 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 310/453 33/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 7692159 m, 21649 m/sec, 206731628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1192 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 315/453 33/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 7712346 m, 4037 m/sec, 210548261 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1197 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 320/453 33/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 7852266 m, 27984 m/sec, 214418695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1202 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 325/453 34/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 8012997 m, 32146 m/sec, 218270249 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1207 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 330/453 35/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 8154089 m, 28218 m/sec, 221664174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1212 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 335/453 35/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 8264873 m, 22156 m/sec, 223945426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1217 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 340/453 36/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 8367399 m, 20505 m/sec, 226246312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1222 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 345/453 36/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 8466964 m, 19913 m/sec, 228530283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1227 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 350/453 36/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 8521049 m, 10817 m/sec, 231588565 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1232 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 355/453 36/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 8521049 m, 0 m/sec, 235773631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1237 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 360/453 37/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 8571057 m, 10001 m/sec, 239881427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1242 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 365/453 37/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 8730798 m, 31948 m/sec, 243585004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1247 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 370/453 38/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 8881751 m, 30190 m/sec, 247324075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1252 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 375/453 38/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 9030387 m, 29727 m/sec, 251161803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1257 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 380/453 39/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 9177810 m, 29484 m/sec, 254974815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1262 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 385/453 40/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-00 9316991 m, 27836 m/sec, 258789560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1267 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9329769
[[35mlola[0m][I] fired transitions : 259172809
[[35mlola[0m][I] time used : 385
[[35mlola[0m][I] memory pages used : 40
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 PhaseVariation-PT-D05CS010-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 466 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 79
[[35mlola[0m][I] fired transitions : 255
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 PhaseVariation-PT-D05CS010-CTLCardinality-2023-13
[[35mlola[0m][I] time limit : 583 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 26
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 40 PhaseVariation-PT-D05CS010-CTLCardinality-2023-12
[[35mlola[0m][I] time limit : 777 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 77
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 PhaseVariation-PT-D05CS010-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 1166 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for PhaseVariation-PT-D05CS010-CTLCardinality-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 26
[[35mlola[0m][I] fired transitions : 52
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05
[[35mlola[0m][I] time limit : 2333 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 5/2333 2/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 247780 m, 49556 m/sec, 3987582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1272 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 10/2333 3/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 506048 m, 51653 m/sec, 8582877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1277 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 15/2333 4/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 746343 m, 48059 m/sec, 13141711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1282 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 20/2333 5/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 971765 m, 45084 m/sec, 17621475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1287 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 25/2333 6/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 1221686 m, 49984 m/sec, 22281747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1292 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 30/2333 7/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 1468594 m, 49381 m/sec, 26823116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1297 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 35/2333 8/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 1695300 m, 45341 m/sec, 31228398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1302 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 40/2333 9/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 1925623 m, 46064 m/sec, 35677930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1307 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 45/2333 10/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 2140362 m, 42947 m/sec, 40124528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1312 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 50/2333 10/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 2357595 m, 43446 m/sec, 44517009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1317 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 55/2333 11/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 2564906 m, 41462 m/sec, 48868056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1322 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 60/2333 12/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 2771898 m, 41398 m/sec, 53287537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1327 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 65/2333 13/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 2963254 m, 38271 m/sec, 57617913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1332 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 70/2333 14/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 3161705 m, 39690 m/sec, 62048169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1337 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 75/2333 15/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 3410372 m, 49733 m/sec, 66503607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1342 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 80/2333 16/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 3645063 m, 46938 m/sec, 70891909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1347 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 85/2333 17/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 3863647 m, 43716 m/sec, 75267123 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1352 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 90/2333 18/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 4093673 m, 46005 m/sec, 79764418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1357 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 95/2333 19/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 4305765 m, 42418 m/sec, 84240274 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1362 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 100/2333 20/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 4525500 m, 43947 m/sec, 88675566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1367 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 105/2333 20/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 4733571 m, 41614 m/sec, 93139644 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1372 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 110/2333 21/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 4939883 m, 41262 m/sec, 97617279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1377 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 115/2333 22/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 5131212 m, 38265 m/sec, 101973680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1382 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 120/2333 23/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 5355562 m, 44870 m/sec, 106351230 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1387 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 125/2333 24/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 5576619 m, 44211 m/sec, 110588804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1392 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 130/2333 25/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 5792431 m, 43162 m/sec, 114779262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1397 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 135/2333 26/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 5999202 m, 41354 m/sec, 118948693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1402 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 140/2333 27/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 6204683 m, 41096 m/sec, 123082116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1407 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 145/2333 27/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 6405751 m, 40213 m/sec, 127172983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1412 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 150/2333 28/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 6584797 m, 35809 m/sec, 131284637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1417 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 155/2333 29/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 6802836 m, 43607 m/sec, 135564258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1422 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 160/2333 30/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 7006605 m, 40753 m/sec, 139810240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1427 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 165/2333 31/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 7206606 m, 40000 m/sec, 144062281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1432 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 170/2333 32/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 7389406 m, 36560 m/sec, 148252910 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1437 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 175/2333 32/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 7576126 m, 37344 m/sec, 152477801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1442 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 180/2333 33/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 7777614 m, 40297 m/sec, 156716931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1447 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 185/2333 34/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 7964253 m, 37327 m/sec, 160896664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1452 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 190/2333 35/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 8144809 m, 36111 m/sec, 165117002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1457 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 195/2333 36/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 8341668 m, 39371 m/sec, 169353091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1462 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 200/2333 36/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 8527418 m, 37150 m/sec, 173624258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1467 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 205/2333 37/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 8714552 m, 37426 m/sec, 177727296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1472 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 210/2333 38/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 8889891 m, 35067 m/sec, 181900256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1477 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 215/2333 39/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 9061902 m, 34402 m/sec, 186123833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1482 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 220/2333 39/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 9228292 m, 33278 m/sec, 190363564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1487 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 225/2333 40/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 9433652 m, 41072 m/sec, 194731558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1492 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 230/2333 41/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 9691786 m, 51626 m/sec, 199253734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1497 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 235/2333 42/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 9928900 m, 47422 m/sec, 203672659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1502 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 240/2333 43/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 10158992 m, 46018 m/sec, 208181761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1507 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 245/2333 44/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 10391775 m, 46556 m/sec, 212693838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1512 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 250/2333 45/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 10613841 m, 44413 m/sec, 217155232 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1517 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 255/2333 46/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 10828884 m, 43008 m/sec, 221514298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1522 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 260/2333 47/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 11033433 m, 40909 m/sec, 225859907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1527 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 265/2333 48/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 11231228 m, 39559 m/sec, 230095295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1532 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 270/2333 49/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 11425978 m, 38950 m/sec, 234421314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1537 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 275/2333 50/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 11669984 m, 48801 m/sec, 238894695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1542 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 280/2333 51/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 11891411 m, 44285 m/sec, 243304595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1547 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 285/2333 51/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 12115560 m, 44829 m/sec, 247600545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1552 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 290/2333 52/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 12325999 m, 42087 m/sec, 251905020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1557 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 295/2333 53/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 12532754 m, 41351 m/sec, 256088150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1562 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 300/2333 54/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 12719528 m, 37354 m/sec, 260303040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1567 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 305/2333 55/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 12945163 m, 45127 m/sec, 264709235 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1572 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 310/2333 56/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 13160898 m, 43147 m/sec, 269120588 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1577 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 315/2333 57/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 13369377 m, 41695 m/sec, 273480956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1582 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 320/2333 58/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 13563025 m, 38729 m/sec, 277839349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1587 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 325/2333 58/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 13757728 m, 38940 m/sec, 282035923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1592 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 330/2333 59/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 13954585 m, 39371 m/sec, 286068963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1597 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 335/2333 60/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 14143414 m, 37765 m/sec, 290052434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1602 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 340/2333 61/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 14324092 m, 36135 m/sec, 294070236 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1607 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 345/2333 61/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 14506821 m, 36545 m/sec, 298053282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1612 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 350/2333 62/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 14684571 m, 35550 m/sec, 302260880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1617 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 355/2333 63/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 14871539 m, 37393 m/sec, 306315972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1622 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 360/2333 64/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 15051282 m, 35948 m/sec, 310387858 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1627 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 365/2333 65/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 15224160 m, 34575 m/sec, 314510614 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1632 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 370/2333 65/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 15390207 m, 33209 m/sec, 318669573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1637 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 375/2333 66/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 15591027 m, 40164 m/sec, 322960444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1642 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 380/2333 67/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 15821288 m, 46052 m/sec, 327311991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1647 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 385/2333 68/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 16033568 m, 42456 m/sec, 331603116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1652 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 390/2333 69/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 16250780 m, 43442 m/sec, 335733154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1657 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 395/2333 70/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 16452482 m, 40340 m/sec, 339883005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1662 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 400/2333 71/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 16652949 m, 40093 m/sec, 343899586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1667 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 405/2333 71/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 16830511 m, 35512 m/sec, 347919695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1672 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 410/2333 72/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 17050480 m, 43993 m/sec, 352287253 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1677 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 415/2333 73/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 17258470 m, 41598 m/sec, 356598587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1682 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 420/2333 74/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 17461215 m, 40549 m/sec, 360869910 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1687 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 425/2333 75/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 17647859 m, 37328 m/sec, 365059549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1692 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 430/2333 75/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 17837969 m, 38022 m/sec, 369261506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1697 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 435/2333 76/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 18039963 m, 40398 m/sec, 373382811 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1702 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 440/2333 77/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 18233739 m, 38755 m/sec, 377387395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1707 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 445/2333 78/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 18418484 m, 36949 m/sec, 381477821 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1712 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 450/2333 79/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 18603388 m, 36980 m/sec, 385517131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1717 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 455/2333 79/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 18771909 m, 33704 m/sec, 389578938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1722 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 460/2333 80/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 18958636 m, 37345 m/sec, 393546970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1727 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 465/2333 81/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 19134294 m, 35131 m/sec, 397461909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1732 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 470/2333 82/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 19303174 m, 33776 m/sec, 401377393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1737 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 475/2333 82/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 19463539 m, 32073 m/sec, 405360543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1742 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 480/2333 83/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 19642711 m, 35834 m/sec, 409419367 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1747 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 485/2333 84/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 19848536 m, 41165 m/sec, 413729389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1752 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 490/2333 85/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 20058850 m, 42062 m/sec, 418021016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1757 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 495/2333 86/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 20260996 m, 40429 m/sec, 422200255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1762 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 500/2333 86/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 20441278 m, 36056 m/sec, 426422731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1767 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 505/2333 87/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 20641341 m, 40012 m/sec, 430571803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1772 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 510/2333 88/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 20842746 m, 40281 m/sec, 434614797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1777 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 515/2333 89/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 21031343 m, 37719 m/sec, 438658517 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1782 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 520/2333 90/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 21217134 m, 37158 m/sec, 442687071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1787 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 525/2333 90/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 21398434 m, 36260 m/sec, 446712609 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1792 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 530/2333 91/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 21573956 m, 35104 m/sec, 450753753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1797 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 535/2333 92/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 21752431 m, 35695 m/sec, 454625562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1802 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 540/2333 93/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 21929367 m, 35387 m/sec, 458530580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1807 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 545/2333 93/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 22097367 m, 33600 m/sec, 462526223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1812 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 550/2333 94/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 22255410 m, 31608 m/sec, 466431059 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1817 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 555/2333 95/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 22453674 m, 39652 m/sec, 470648695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1822 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 560/2333 96/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 22650073 m, 39279 m/sec, 474870550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1827 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 565/2333 96/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 22832441 m, 36473 m/sec, 479060499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1832 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 570/2333 97/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 23023820 m, 38275 m/sec, 483277568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1837 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 575/2333 98/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 23217544 m, 38744 m/sec, 487465072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1842 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 580/2333 99/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 23400412 m, 36573 m/sec, 491662455 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1847 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 585/2333 100/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 23580484 m, 36014 m/sec, 495672964 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1852 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 590/2333 100/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 23758617 m, 35626 m/sec, 499783395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1857 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-11: CONJ false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-12: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PhaseVariation-PT-D05CS010-CTLCardinality-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 595/2333 101/2000 PhaseVariation-PT-D05CS010-CTLCardinality-2024-05 23927767 m, 33830 m/sec, 503929049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1862 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPhaseVariation-PT-D05CS010-CTLCardinality-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPhaseVariation-PT-D05CS010-CTLCardinality-2024-04: CTL true CTL model checker[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PhaseVariation-PT-D05CS010"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PhaseVariation-PT-D05CS010, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408600313"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PhaseVariation-PT-D05CS010.tgz
mv PhaseVariation-PT-D05CS010 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;