About the Execution of LoLA for PermAdmissibility-PT-02
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
14383.239 | 3600000.00 | 3677713.00 | 10723.10 | ?F????TF??????F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408300163.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PermAdmissibility-PT-02, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408300163
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.8M
-rw-r--r-- 1 mcc users 11K Apr 12 09:11 CTLCardinality.txt
-rw-r--r-- 1 mcc users 102K Apr 12 09:11 CTLCardinality.xml
-rw-r--r-- 1 mcc users 52K Apr 12 09:09 CTLFireability.txt
-rw-r--r-- 1 mcc users 268K Apr 12 09:09 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 18K Apr 23 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 72K Apr 23 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Apr 12 09:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 154K Apr 12 09:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 113K Apr 12 09:17 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 575K Apr 12 09:17 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.4K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 336K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-00
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-01
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-02
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-03
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-04
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-05
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-06
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-07
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-08
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-09
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-10
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-11
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-12
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-13
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-14
FORMULA_NAME PermAdmissibility-PT-02-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717093320039
FORMULA PermAdmissibility-PT-02-LTLCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-LTLCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-LTLCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-LTLCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 6 (type CNST) for 3 PermAdmissibility-PT-02-LTLCardinality-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 6 (type CNST) for PermAdmissibility-PT-02-LTLCardinality-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 78 (type SKEL/FNDP) for 25 PermAdmissibility-PT-02-LTLCardinality-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 79 (type SKEL/EQUN) for 25 PermAdmissibility-PT-02-LTLCardinality-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 80 (type SKEL/SRCH) for 25 PermAdmissibility-PT-02-LTLCardinality-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 80 (type SKEL/SRCH) for PermAdmissibility-PT-02-LTLCardinality-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 78 (type FNDP) for PermAdmissibility-PT-02-LTLCardinality-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 79 (type EQUN) for PermAdmissibility-PT-02-LTLCardinality-07 (obsolete)
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 78 (type SKEL/FNDP) for PermAdmissibility-PT-02-LTLCardinality-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 79 (type SKEL/EQUN) for PermAdmissibility-PT-02-LTLCardinality-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 42 (type CNST) for 39 PermAdmissibility-PT-02-LTLCardinality-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 42 (type CNST) for PermAdmissibility-PT-02-LTLCardinality-09
[[35mlola[0m][I] result : true
[*** LOG ERROR #0001 ***] [2024-05-30 18:22:02] [status_logger] string pointer is null
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 81 (type SKEL/SRCH) for 46 PermAdmissibility-PT-02-LTLCardinality-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 81 (type SKEL/SRCH) for PermAdmissibility-PT-02-LTLCardinality-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type CNST) for 25 PermAdmissibility-PT-02-LTLCardinality-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 28 (type CNST) for PermAdmissibility-PT-02-LTLCardinality-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 PermAdmissibility-PT-02-LTLCardinality-06
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 30
[[35mlola[0m][I] fired transitions : 36
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 PermAdmissibility-PT-02-LTLCardinality-03
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 69 (type CNST) for 66 PermAdmissibility-PT-02-LTLCardinality-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 69 (type CNST) for PermAdmissibility-PT-02-LTLCardinality-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 86 (type EQUN) for 49 PermAdmissibility-PT-02-LTLCardinality-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 90 (type EQUN) for 49 PermAdmissibility-PT-02-LTLCardinality-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 86 (type EQUN) for PermAdmissibility-PT-02-LTLCardinality-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 90 (type EQUN) for PermAdmissibility-PT-02-LTLCardinality-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 5/257 7/2000 PermAdmissibility-PT-02-LTLCardinality-03 1022221 m, 204444 m/sec, 1471461 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 7 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 10/257 15/2000 PermAdmissibility-PT-02-LTLCardinality-03 2111160 m, 217787 m/sec, 3122846 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 12 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 15/257 22/2000 PermAdmissibility-PT-02-LTLCardinality-03 3198563 m, 217480 m/sec, 4755888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 17 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 20/257 29/2000 PermAdmissibility-PT-02-LTLCardinality-03 4253280 m, 210943 m/sec, 6379566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 22 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 25/257 36/2000 PermAdmissibility-PT-02-LTLCardinality-03 5268072 m, 202958 m/sec, 7982946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 27 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 30/257 42/2000 PermAdmissibility-PT-02-LTLCardinality-03 6255235 m, 197432 m/sec, 9574198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 32 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 35/257 49/2000 PermAdmissibility-PT-02-LTLCardinality-03 7241127 m, 197178 m/sec, 11094932 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 37 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 40/257 56/2000 PermAdmissibility-PT-02-LTLCardinality-03 8242606 m, 200295 m/sec, 12653186 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 42 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 45/257 62/2000 PermAdmissibility-PT-02-LTLCardinality-03 9249583 m, 201395 m/sec, 14283719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 47 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 50/257 69/2000 PermAdmissibility-PT-02-LTLCardinality-03 10219795 m, 194042 m/sec, 15915956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 52 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 55/257 75/2000 PermAdmissibility-PT-02-LTLCardinality-03 11178944 m, 191829 m/sec, 17523066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 57 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 60/257 81/2000 PermAdmissibility-PT-02-LTLCardinality-03 12080102 m, 180231 m/sec, 19166241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 62 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 65/257 86/2000 PermAdmissibility-PT-02-LTLCardinality-03 12788503 m, 141680 m/sec, 21039125 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 67 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 70/257 93/2000 PermAdmissibility-PT-02-LTLCardinality-03 13867718 m, 215843 m/sec, 22729112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 72 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 75/257 100/2000 PermAdmissibility-PT-02-LTLCardinality-03 14886239 m, 203704 m/sec, 24363239 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 77 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 80/257 106/2000 PermAdmissibility-PT-02-LTLCardinality-03 15877232 m, 198198 m/sec, 25940606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 82 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 85/257 113/2000 PermAdmissibility-PT-02-LTLCardinality-03 16830869 m, 190727 m/sec, 27508216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 87 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 90/257 119/2000 PermAdmissibility-PT-02-LTLCardinality-03 17810738 m, 195973 m/sec, 29147098 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 92 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 95/257 126/2000 PermAdmissibility-PT-02-LTLCardinality-03 18741432 m, 186138 m/sec, 30732196 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 97 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 100/257 132/2000 PermAdmissibility-PT-02-LTLCardinality-03 19650251 m, 181763 m/sec, 32307279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 102 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 105/257 137/2000 PermAdmissibility-PT-02-LTLCardinality-03 20501817 m, 170313 m/sec, 33961108 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 107 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 110/257 142/2000 PermAdmissibility-PT-02-LTLCardinality-03 21268188 m, 153274 m/sec, 35775541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 112 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 115/257 148/2000 PermAdmissibility-PT-02-LTLCardinality-03 22156103 m, 177583 m/sec, 37454106 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 117 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 120/257 154/2000 PermAdmissibility-PT-02-LTLCardinality-03 23084188 m, 185617 m/sec, 39031903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 122 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 125/257 160/2000 PermAdmissibility-PT-02-LTLCardinality-03 23899274 m, 163017 m/sec, 40703158 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 127 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 130/257 165/2000 PermAdmissibility-PT-02-LTLCardinality-03 24670297 m, 154204 m/sec, 42393793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 132 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 135/257 168/2000 PermAdmissibility-PT-02-LTLCardinality-03 25052930 m, 76526 m/sec, 44586284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 137 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 140/257 171/2000 PermAdmissibility-PT-02-LTLCardinality-03 25584890 m, 106392 m/sec, 46691225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 142 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 145/257 178/2000 PermAdmissibility-PT-02-LTLCardinality-03 26566662 m, 196354 m/sec, 48208924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 147 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 150/257 184/2000 PermAdmissibility-PT-02-LTLCardinality-03 27508362 m, 188340 m/sec, 49715416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 152 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 155/257 190/2000 PermAdmissibility-PT-02-LTLCardinality-03 28369699 m, 172267 m/sec, 51280711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 157 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 160/257 196/2000 PermAdmissibility-PT-02-LTLCardinality-03 29246821 m, 175424 m/sec, 52866560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 162 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 165/257 201/2000 PermAdmissibility-PT-02-LTLCardinality-03 30118091 m, 174254 m/sec, 54381574 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 167 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 170/257 207/2000 PermAdmissibility-PT-02-LTLCardinality-03 30918009 m, 159983 m/sec, 55961068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 172 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 175/257 211/2000 PermAdmissibility-PT-02-LTLCardinality-03 31497258 m, 115849 m/sec, 57837268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 177 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 180/257 217/2000 PermAdmissibility-PT-02-LTLCardinality-03 32403889 m, 181326 m/sec, 59509728 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 182 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 185/257 223/2000 PermAdmissibility-PT-02-LTLCardinality-03 33333947 m, 186011 m/sec, 61030269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 187 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 190/257 229/2000 PermAdmissibility-PT-02-LTLCardinality-03 34229540 m, 179118 m/sec, 62529766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 192 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 195/257 235/2000 PermAdmissibility-PT-02-LTLCardinality-03 35085350 m, 171162 m/sec, 64134132 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 197 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 200/257 240/2000 PermAdmissibility-PT-02-LTLCardinality-03 35960818 m, 175093 m/sec, 65651665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 202 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 205/257 246/2000 PermAdmissibility-PT-02-LTLCardinality-03 36776995 m, 163235 m/sec, 67216829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 207 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 210/257 250/2000 PermAdmissibility-PT-02-LTLCardinality-03 37372727 m, 119146 m/sec, 69016896 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 212 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 215/257 255/2000 PermAdmissibility-PT-02-LTLCardinality-03 38157031 m, 156860 m/sec, 70760328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 217 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 220/257 260/2000 PermAdmissibility-PT-02-LTLCardinality-03 38895220 m, 147637 m/sec, 72334926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 222 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 225/257 265/2000 PermAdmissibility-PT-02-LTLCardinality-03 39602200 m, 141396 m/sec, 74234363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 227 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 230/257 272/2000 PermAdmissibility-PT-02-LTLCardinality-03 40590008 m, 197561 m/sec, 75754294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 232 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 235/257 278/2000 PermAdmissibility-PT-02-LTLCardinality-03 41515895 m, 185177 m/sec, 77255217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 237 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 240/257 283/2000 PermAdmissibility-PT-02-LTLCardinality-03 42356294 m, 168079 m/sec, 78865191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 242 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 245/257 290/2000 PermAdmissibility-PT-02-LTLCardinality-03 43282914 m, 185324 m/sec, 80385834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 247 secs. Pages in use: 290
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 250/257 295/2000 PermAdmissibility-PT-02-LTLCardinality-03 44101685 m, 163754 m/sec, 81948617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 252 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 255/257 300/2000 PermAdmissibility-PT-02-LTLCardinality-03 44839329 m, 147528 m/sec, 83565978 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 257 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 14 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-03 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 262 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 74 (type EXCL) for 73 PermAdmissibility-PT-02-LTLCardinality-15
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 PermAdmissibility-PT-02-LTLCardinality-03
[[35mlola[0m][I] time limit : 3338 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 33
[[35mlola[0m][I] fired transitions : 33
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 14 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-03 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-09: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 267 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL) for 63 PermAdmissibility-PT-02-LTLCardinality-13
[[35mlola[0m][I] time limit : 277 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 64 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 56 PermAdmissibility-PT-02-LTLCardinality-12
[[35mlola[0m][I] time limit : 303 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 PermAdmissibility-PT-02-LTLCardinality-10
[[35mlola[0m][I] time limit : 333 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 39 PermAdmissibility-PT-02-LTLCardinality-09
[[35mlola[0m][I] time limit : 370 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8950
[[35mlola[0m][I] fired transitions : 33310
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 PermAdmissibility-PT-02-LTLCardinality-05
[[35mlola[0m][I] time limit : 416 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 5/416 8/2000 PermAdmissibility-PT-02-LTLCardinality-05 1024064 m, 204812 m/sec, 1360678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 272 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 10/416 14/2000 PermAdmissibility-PT-02-LTLCardinality-05 1984309 m, 192049 m/sec, 3207331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 277 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 15/416 20/2000 PermAdmissibility-PT-02-LTLCardinality-05 2821725 m, 167483 m/sec, 5307569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 282 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 20/416 25/2000 PermAdmissibility-PT-02-LTLCardinality-05 3547311 m, 145117 m/sec, 7728724 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 287 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-11: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 25/416 29/2000 PermAdmissibility-PT-02-LTLCardinality-05 4230648 m, 136667 m/sec, 10223407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4427216
[[35mlola[0m][I] fired transitions : 10964350
[[35mlola[0m][I] time used : 27
[[35mlola[0m][I] memory pages used : 30
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 PermAdmissibility-PT-02-LTLCardinality-00
[[35mlola[0m][I] time limit : 472 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 33
[[35mlola[0m][I] fired transitions : 33
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 87 (type EXCL) for 49 PermAdmissibility-PT-02-LTLCardinality-11
[[35mlola[0m][I] time limit : 551 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 87 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 33
[[35mlola[0m][I] fired transitions : 32
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 PermAdmissibility-PT-02-LTLCardinality-02
[[35mlola[0m][I] time limit : 826 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 3/826 1/2000 PermAdmissibility-PT-02-LTLCardinality-02 65665 m, 13133 m/sec, 516770 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 8/826 2/2000 PermAdmissibility-PT-02-LTLCardinality-02 179938 m, 22854 m/sec, 1428121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 13/826 3/2000 PermAdmissibility-PT-02-LTLCardinality-02 323547 m, 28721 m/sec, 2375897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 18/826 4/2000 PermAdmissibility-PT-02-LTLCardinality-02 477429 m, 30776 m/sec, 3313902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 23/826 5/2000 PermAdmissibility-PT-02-LTLCardinality-02 631981 m, 30910 m/sec, 4228655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 28/826 5/2000 PermAdmissibility-PT-02-LTLCardinality-02 738439 m, 21291 m/sec, 5089926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 33/826 6/2000 PermAdmissibility-PT-02-LTLCardinality-02 856380 m, 23588 m/sec, 6021459 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 38/826 7/2000 PermAdmissibility-PT-02-LTLCardinality-02 988613 m, 26446 m/sec, 6955578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 43/826 8/2000 PermAdmissibility-PT-02-LTLCardinality-02 1122430 m, 26763 m/sec, 8007131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 48/826 9/2000 PermAdmissibility-PT-02-LTLCardinality-02 1284161 m, 32346 m/sec, 8980331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 53/826 10/2000 PermAdmissibility-PT-02-LTLCardinality-02 1441213 m, 31410 m/sec, 9909625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 58/826 11/2000 PermAdmissibility-PT-02-LTLCardinality-02 1600477 m, 31852 m/sec, 10872389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 63/826 12/2000 PermAdmissibility-PT-02-LTLCardinality-02 1773472 m, 34599 m/sec, 11827355 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 68/826 13/2000 PermAdmissibility-PT-02-LTLCardinality-02 1936469 m, 32599 m/sec, 12781100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 73/826 14/2000 PermAdmissibility-PT-02-LTLCardinality-02 2121469 m, 37000 m/sec, 13664775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 78/826 16/2000 PermAdmissibility-PT-02-LTLCardinality-02 2281473 m, 32000 m/sec, 14558978 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 83/826 17/2000 PermAdmissibility-PT-02-LTLCardinality-02 2440665 m, 31838 m/sec, 15482745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 88/826 18/2000 PermAdmissibility-PT-02-LTLCardinality-02 2621744 m, 36215 m/sec, 16346263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 93/826 19/2000 PermAdmissibility-PT-02-LTLCardinality-02 2785175 m, 32686 m/sec, 17231738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 98/826 20/2000 PermAdmissibility-PT-02-LTLCardinality-02 2965102 m, 35985 m/sec, 18107207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 103/826 21/2000 PermAdmissibility-PT-02-LTLCardinality-02 3149098 m, 36799 m/sec, 18930791 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 108/826 22/2000 PermAdmissibility-PT-02-LTLCardinality-02 3336621 m, 37504 m/sec, 19732742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 113/826 24/2000 PermAdmissibility-PT-02-LTLCardinality-02 3496758 m, 32027 m/sec, 20709964 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 118/826 25/2000 PermAdmissibility-PT-02-LTLCardinality-02 3665698 m, 33788 m/sec, 21711476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 123/826 26/2000 PermAdmissibility-PT-02-LTLCardinality-02 3845343 m, 35929 m/sec, 22660304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 128/826 27/2000 PermAdmissibility-PT-02-LTLCardinality-02 4012391 m, 33409 m/sec, 23683709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 133/826 28/2000 PermAdmissibility-PT-02-LTLCardinality-02 4182114 m, 33944 m/sec, 24652760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 138/826 29/2000 PermAdmissibility-PT-02-LTLCardinality-02 4357886 m, 35154 m/sec, 25599408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 143/826 30/2000 PermAdmissibility-PT-02-LTLCardinality-02 4539145 m, 36251 m/sec, 26540315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 148/826 32/2000 PermAdmissibility-PT-02-LTLCardinality-02 4712971 m, 34765 m/sec, 27460413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 153/826 33/2000 PermAdmissibility-PT-02-LTLCardinality-02 4873118 m, 32029 m/sec, 28505610 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 158/826 34/2000 PermAdmissibility-PT-02-LTLCardinality-02 5048977 m, 35171 m/sec, 29536714 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 163/826 35/2000 PermAdmissibility-PT-02-LTLCardinality-02 5226452 m, 35495 m/sec, 30537162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 168/826 36/2000 PermAdmissibility-PT-02-LTLCardinality-02 5397454 m, 34200 m/sec, 31505043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 173/826 37/2000 PermAdmissibility-PT-02-LTLCardinality-02 5570715 m, 34652 m/sec, 32587230 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 467 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 178/826 38/2000 PermAdmissibility-PT-02-LTLCardinality-02 5751543 m, 36165 m/sec, 33539134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 472 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 183/826 40/2000 PermAdmissibility-PT-02-LTLCardinality-02 5919437 m, 33578 m/sec, 34517242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 477 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 188/826 41/2000 PermAdmissibility-PT-02-LTLCardinality-02 6099593 m, 36031 m/sec, 35421830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 482 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 193/826 42/2000 PermAdmissibility-PT-02-LTLCardinality-02 6270141 m, 34109 m/sec, 36419100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 487 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 198/826 43/2000 PermAdmissibility-PT-02-LTLCardinality-02 6450386 m, 36049 m/sec, 37360876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 492 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 203/826 44/2000 PermAdmissibility-PT-02-LTLCardinality-02 6634365 m, 36795 m/sec, 38209057 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 497 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 208/826 46/2000 PermAdmissibility-PT-02-LTLCardinality-02 6816730 m, 36473 m/sec, 39131320 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 502 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 213/826 47/2000 PermAdmissibility-PT-02-LTLCardinality-02 6994047 m, 35463 m/sec, 40088036 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 507 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 218/826 48/2000 PermAdmissibility-PT-02-LTLCardinality-02 7175068 m, 36204 m/sec, 40996035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 512 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 223/826 49/2000 PermAdmissibility-PT-02-LTLCardinality-02 7359204 m, 36827 m/sec, 41867995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 517 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 228/826 50/2000 PermAdmissibility-PT-02-LTLCardinality-02 7535815 m, 35322 m/sec, 42785786 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 522 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 233/826 51/2000 PermAdmissibility-PT-02-LTLCardinality-02 7718634 m, 36563 m/sec, 43713420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 527 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 238/826 53/2000 PermAdmissibility-PT-02-LTLCardinality-02 7905915 m, 37456 m/sec, 44527751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 532 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 243/826 54/2000 PermAdmissibility-PT-02-LTLCardinality-02 8092496 m, 37316 m/sec, 45265955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 537 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 248/826 55/2000 PermAdmissibility-PT-02-LTLCardinality-02 8276617 m, 36824 m/sec, 46141756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 542 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 253/826 56/2000 PermAdmissibility-PT-02-LTLCardinality-02 8457920 m, 36260 m/sec, 47069437 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 547 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 258/826 58/2000 PermAdmissibility-PT-02-LTLCardinality-02 8646402 m, 37696 m/sec, 47958732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 552 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 263/826 59/2000 PermAdmissibility-PT-02-LTLCardinality-02 8824797 m, 35679 m/sec, 48869849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 557 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 268/826 60/2000 PermAdmissibility-PT-02-LTLCardinality-02 9003306 m, 35701 m/sec, 49713631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 562 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 273/826 61/2000 PermAdmissibility-PT-02-LTLCardinality-02 9186311 m, 36601 m/sec, 50567730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 567 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 278/826 62/2000 PermAdmissibility-PT-02-LTLCardinality-02 9373662 m, 37470 m/sec, 51408641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 572 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 283/826 64/2000 PermAdmissibility-PT-02-LTLCardinality-02 9561706 m, 37608 m/sec, 52226787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 288/826 65/2000 PermAdmissibility-PT-02-LTLCardinality-02 9752075 m, 38073 m/sec, 53046122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 582 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 293/826 66/2000 PermAdmissibility-PT-02-LTLCardinality-02 9938945 m, 37374 m/sec, 53804096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 587 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 298/826 67/2000 PermAdmissibility-PT-02-LTLCardinality-02 10124961 m, 37203 m/sec, 54558144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 592 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 303/826 69/2000 PermAdmissibility-PT-02-LTLCardinality-02 10312978 m, 37603 m/sec, 55366518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 597 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 308/826 70/2000 PermAdmissibility-PT-02-LTLCardinality-02 10503573 m, 38119 m/sec, 56127407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 602 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 313/826 71/2000 PermAdmissibility-PT-02-LTLCardinality-02 10690125 m, 37310 m/sec, 56838420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 607 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 318/826 72/2000 PermAdmissibility-PT-02-LTLCardinality-02 10878963 m, 37767 m/sec, 57583404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 612 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 323/826 74/2000 PermAdmissibility-PT-02-LTLCardinality-02 11063741 m, 36955 m/sec, 58363612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 617 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 328/826 75/2000 PermAdmissibility-PT-02-LTLCardinality-02 11252240 m, 37699 m/sec, 59261097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 622 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 333/826 76/2000 PermAdmissibility-PT-02-LTLCardinality-02 11436389 m, 36829 m/sec, 60181216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 627 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 338/826 77/2000 PermAdmissibility-PT-02-LTLCardinality-02 11627411 m, 38204 m/sec, 61074326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 632 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 343/826 79/2000 PermAdmissibility-PT-02-LTLCardinality-02 11820558 m, 38629 m/sec, 61936762 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 637 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 348/826 80/2000 PermAdmissibility-PT-02-LTLCardinality-02 12014191 m, 38726 m/sec, 62797826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 642 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 353/826 81/2000 PermAdmissibility-PT-02-LTLCardinality-02 12209190 m, 38999 m/sec, 63647730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 647 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 358/826 83/2000 PermAdmissibility-PT-02-LTLCardinality-02 12405928 m, 39347 m/sec, 64440223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 652 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 363/826 84/2000 PermAdmissibility-PT-02-LTLCardinality-02 12588344 m, 36483 m/sec, 65336319 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 657 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 368/826 85/2000 PermAdmissibility-PT-02-LTLCardinality-02 12776444 m, 37620 m/sec, 66169027 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 662 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 373/826 86/2000 PermAdmissibility-PT-02-LTLCardinality-02 12966689 m, 38049 m/sec, 66965472 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 667 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 378/826 88/2000 PermAdmissibility-PT-02-LTLCardinality-02 13156197 m, 37901 m/sec, 67813828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 672 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 383/826 89/2000 PermAdmissibility-PT-02-LTLCardinality-02 13347706 m, 38301 m/sec, 68606695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 677 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 388/826 90/2000 PermAdmissibility-PT-02-LTLCardinality-02 13536621 m, 37783 m/sec, 69436185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 682 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 393/826 91/2000 PermAdmissibility-PT-02-LTLCardinality-02 13712537 m, 35183 m/sec, 70317256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 687 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 398/826 92/2000 PermAdmissibility-PT-02-LTLCardinality-02 13894802 m, 36453 m/sec, 71134662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 692 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 403/826 94/2000 PermAdmissibility-PT-02-LTLCardinality-02 14080208 m, 37081 m/sec, 71936432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 697 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 408/826 95/2000 PermAdmissibility-PT-02-LTLCardinality-02 14274393 m, 38837 m/sec, 72756062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 702 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 413/826 96/2000 PermAdmissibility-PT-02-LTLCardinality-02 14468277 m, 38776 m/sec, 73500918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 707 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 418/826 97/2000 PermAdmissibility-PT-02-LTLCardinality-02 14655566 m, 37457 m/sec, 74318385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 712 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 423/826 99/2000 PermAdmissibility-PT-02-LTLCardinality-02 14838439 m, 36574 m/sec, 75143926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 717 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 428/826 100/2000 PermAdmissibility-PT-02-LTLCardinality-02 15029737 m, 38259 m/sec, 76001398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 722 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 433/826 101/2000 PermAdmissibility-PT-02-LTLCardinality-02 15216857 m, 37424 m/sec, 76855246 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 727 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 438/826 102/2000 PermAdmissibility-PT-02-LTLCardinality-02 15402730 m, 37174 m/sec, 77633809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 732 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 443/826 104/2000 PermAdmissibility-PT-02-LTLCardinality-02 15596943 m, 38842 m/sec, 78464352 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 737 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 448/826 105/2000 PermAdmissibility-PT-02-LTLCardinality-02 15784403 m, 37492 m/sec, 79314806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 742 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 453/826 106/2000 PermAdmissibility-PT-02-LTLCardinality-02 15968503 m, 36820 m/sec, 80106407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 747 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 458/826 107/2000 PermAdmissibility-PT-02-LTLCardinality-02 16159943 m, 38288 m/sec, 80843096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 752 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 463/826 109/2000 PermAdmissibility-PT-02-LTLCardinality-02 16350434 m, 38098 m/sec, 81595785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 757 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 468/826 110/2000 PermAdmissibility-PT-02-LTLCardinality-02 16535377 m, 36988 m/sec, 82349929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 762 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 473/826 111/2000 PermAdmissibility-PT-02-LTLCardinality-02 16726787 m, 38282 m/sec, 83169938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 478/826 113/2000 PermAdmissibility-PT-02-LTLCardinality-02 16920234 m, 38689 m/sec, 83931220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 772 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 483/826 114/2000 PermAdmissibility-PT-02-LTLCardinality-02 17115133 m, 38979 m/sec, 84656247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 777 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 488/826 115/2000 PermAdmissibility-PT-02-LTLCardinality-02 17300857 m, 37144 m/sec, 85500180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 782 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 493/826 116/2000 PermAdmissibility-PT-02-LTLCardinality-02 17483881 m, 36604 m/sec, 86332483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 787 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 498/826 117/2000 PermAdmissibility-PT-02-LTLCardinality-02 17668289 m, 36881 m/sec, 87161686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 503/826 119/2000 PermAdmissibility-PT-02-LTLCardinality-02 17854661 m, 37274 m/sec, 87966999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 797 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 508/826 120/2000 PermAdmissibility-PT-02-LTLCardinality-02 18036474 m, 36362 m/sec, 88689146 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 802 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 513/826 121/2000 PermAdmissibility-PT-02-LTLCardinality-02 18228348 m, 38374 m/sec, 89490093 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 807 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 518/826 122/2000 PermAdmissibility-PT-02-LTLCardinality-02 18414109 m, 37152 m/sec, 90213509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 812 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 523/826 124/2000 PermAdmissibility-PT-02-LTLCardinality-02 18597888 m, 36755 m/sec, 90922974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 817 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 528/826 125/2000 PermAdmissibility-PT-02-LTLCardinality-02 18787772 m, 37976 m/sec, 91725209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 822 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 533/826 126/2000 PermAdmissibility-PT-02-LTLCardinality-02 18976970 m, 37839 m/sec, 92544604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 827 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 538/826 127/2000 PermAdmissibility-PT-02-LTLCardinality-02 19163481 m, 37302 m/sec, 93410751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 832 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 543/826 129/2000 PermAdmissibility-PT-02-LTLCardinality-02 19352141 m, 37732 m/sec, 94283038 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 837 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 548/826 130/2000 PermAdmissibility-PT-02-LTLCardinality-02 19544481 m, 38468 m/sec, 95123575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 842 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 553/826 131/2000 PermAdmissibility-PT-02-LTLCardinality-02 19736906 m, 38485 m/sec, 95932788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 847 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 558/826 132/2000 PermAdmissibility-PT-02-LTLCardinality-02 19930165 m, 38651 m/sec, 96768027 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 852 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 563/826 134/2000 PermAdmissibility-PT-02-LTLCardinality-02 20118170 m, 37601 m/sec, 97614203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 857 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 568/826 135/2000 PermAdmissibility-PT-02-LTLCardinality-02 20305466 m, 37459 m/sec, 98406129 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 862 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 573/826 136/2000 PermAdmissibility-PT-02-LTLCardinality-02 20490311 m, 36969 m/sec, 99221778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 867 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 578/826 137/2000 PermAdmissibility-PT-02-LTLCardinality-02 20673641 m, 36666 m/sec, 100059102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 872 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 583/826 139/2000 PermAdmissibility-PT-02-LTLCardinality-02 20852772 m, 35826 m/sec, 100779211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 877 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 588/826 140/2000 PermAdmissibility-PT-02-LTLCardinality-02 21041034 m, 37652 m/sec, 101549905 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 882 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 593/826 141/2000 PermAdmissibility-PT-02-LTLCardinality-02 21230239 m, 37841 m/sec, 102315910 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 887 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 598/826 142/2000 PermAdmissibility-PT-02-LTLCardinality-02 21417021 m, 37356 m/sec, 103076100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 892 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 603/826 143/2000 PermAdmissibility-PT-02-LTLCardinality-02 21599848 m, 36565 m/sec, 103806160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 897 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 608/826 145/2000 PermAdmissibility-PT-02-LTLCardinality-02 21791251 m, 38280 m/sec, 104611732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 902 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 613/826 146/2000 PermAdmissibility-PT-02-LTLCardinality-02 21973628 m, 36475 m/sec, 105413478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 907 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 618/826 147/2000 PermAdmissibility-PT-02-LTLCardinality-02 22160798 m, 37434 m/sec, 106210813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 912 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 623/826 148/2000 PermAdmissibility-PT-02-LTLCardinality-02 22351441 m, 38128 m/sec, 106989482 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 917 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 628/826 150/2000 PermAdmissibility-PT-02-LTLCardinality-02 22536524 m, 37016 m/sec, 107743430 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 922 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 633/826 151/2000 PermAdmissibility-PT-02-LTLCardinality-02 22723049 m, 37305 m/sec, 108462155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 927 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 638/826 152/2000 PermAdmissibility-PT-02-LTLCardinality-02 22910073 m, 37404 m/sec, 109205580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 932 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 643/826 153/2000 PermAdmissibility-PT-02-LTLCardinality-02 23102481 m, 38481 m/sec, 109974776 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 937 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 648/826 155/2000 PermAdmissibility-PT-02-LTLCardinality-02 23292067 m, 37917 m/sec, 110706271 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 942 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 653/826 156/2000 PermAdmissibility-PT-02-LTLCardinality-02 23488913 m, 39369 m/sec, 111469586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 947 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 658/826 157/2000 PermAdmissibility-PT-02-LTLCardinality-02 23686752 m, 39567 m/sec, 112249080 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 952 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 663/826 159/2000 PermAdmissibility-PT-02-LTLCardinality-02 23883097 m, 39269 m/sec, 113004082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 957 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 668/826 160/2000 PermAdmissibility-PT-02-LTLCardinality-02 24075763 m, 38533 m/sec, 113723784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 962 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 673/826 161/2000 PermAdmissibility-PT-02-LTLCardinality-02 24267979 m, 38443 m/sec, 114444873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 967 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 678/826 162/2000 PermAdmissibility-PT-02-LTLCardinality-02 24461829 m, 38770 m/sec, 115112105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 972 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 683/826 164/2000 PermAdmissibility-PT-02-LTLCardinality-02 24650054 m, 37645 m/sec, 115817775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 977 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 688/826 165/2000 PermAdmissibility-PT-02-LTLCardinality-02 24843329 m, 38655 m/sec, 116554226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 982 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 693/826 166/2000 PermAdmissibility-PT-02-LTLCardinality-02 25028618 m, 37057 m/sec, 117265394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 987 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 698/826 167/2000 PermAdmissibility-PT-02-LTLCardinality-02 25218242 m, 37924 m/sec, 117939366 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 992 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 703/826 169/2000 PermAdmissibility-PT-02-LTLCardinality-02 25409405 m, 38232 m/sec, 118646887 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 997 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 708/826 170/2000 PermAdmissibility-PT-02-LTLCardinality-02 25600183 m, 38155 m/sec, 119363490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1002 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 713/826 171/2000 PermAdmissibility-PT-02-LTLCardinality-02 25792696 m, 38502 m/sec, 120112710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1007 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 718/826 172/2000 PermAdmissibility-PT-02-LTLCardinality-02 25978578 m, 37176 m/sec, 120818008 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1012 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 723/826 174/2000 PermAdmissibility-PT-02-LTLCardinality-02 26171934 m, 38671 m/sec, 121526061 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1017 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 728/826 175/2000 PermAdmissibility-PT-02-LTLCardinality-02 26355834 m, 36780 m/sec, 122236402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1022 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 733/826 176/2000 PermAdmissibility-PT-02-LTLCardinality-02 26550463 m, 38925 m/sec, 122975295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1027 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 738/826 177/2000 PermAdmissibility-PT-02-LTLCardinality-02 26740817 m, 38070 m/sec, 123697665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1032 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 743/826 179/2000 PermAdmissibility-PT-02-LTLCardinality-02 26929914 m, 37819 m/sec, 124393888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1037 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 748/826 180/2000 PermAdmissibility-PT-02-LTLCardinality-02 27116679 m, 37353 m/sec, 125059535 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1042 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 753/826 181/2000 PermAdmissibility-PT-02-LTLCardinality-02 27308747 m, 38413 m/sec, 125769989 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1047 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 758/826 183/2000 PermAdmissibility-PT-02-LTLCardinality-02 27502893 m, 38829 m/sec, 126445474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1052 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 763/826 184/2000 PermAdmissibility-PT-02-LTLCardinality-02 27693677 m, 38156 m/sec, 127095596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1057 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 768/826 185/2000 PermAdmissibility-PT-02-LTLCardinality-02 27881917 m, 37648 m/sec, 127760997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1062 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 773/826 186/2000 PermAdmissibility-PT-02-LTLCardinality-02 28067939 m, 37204 m/sec, 128424693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1067 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 778/826 187/2000 PermAdmissibility-PT-02-LTLCardinality-02 28254920 m, 37396 m/sec, 129069310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1072 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 783/826 189/2000 PermAdmissibility-PT-02-LTLCardinality-02 28444233 m, 37862 m/sec, 129788655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1077 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 788/826 190/2000 PermAdmissibility-PT-02-LTLCardinality-02 28631521 m, 37457 m/sec, 130469842 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1082 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 793/826 191/2000 PermAdmissibility-PT-02-LTLCardinality-02 28819080 m, 37511 m/sec, 131184490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1087 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 798/826 192/2000 PermAdmissibility-PT-02-LTLCardinality-02 29006043 m, 37392 m/sec, 131847757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1092 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 803/826 194/2000 PermAdmissibility-PT-02-LTLCardinality-02 29195334 m, 37858 m/sec, 132519769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1097 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 808/826 195/2000 PermAdmissibility-PT-02-LTLCardinality-02 29384457 m, 37824 m/sec, 133177421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1102 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 813/826 196/2000 PermAdmissibility-PT-02-LTLCardinality-02 29571349 m, 37378 m/sec, 133835475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1107 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 818/826 197/2000 PermAdmissibility-PT-02-LTLCardinality-02 29756060 m, 36942 m/sec, 134479526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1112 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 823/826 199/2000 PermAdmissibility-PT-02-LTLCardinality-02 29944299 m, 37647 m/sec, 135126672 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1117 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 11 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1122 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 56 PermAdmissibility-PT-02-LTLCardinality-12
[[35mlola[0m][I] time limit : 826 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 PermAdmissibility-PT-02-LTLCardinality-02
[[35mlola[0m][I] time limit : 2478 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 5/2478 1/5 PermAdmissibility-PT-02-LTLCardinality-02 99020 m, -5969055 m/sec, 807203 t fired, .
[[35mlola[0m][.] 61 LTL EXCL 5/826 1/2000 PermAdmissibility-PT-02-LTLCardinality-12 123602 m, 24720 m/sec, 586275 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1127 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 10/2478 2/5 PermAdmissibility-PT-02-LTLCardinality-02 222407 m, 24677 m/sec, 1745354 t fired, .
[[35mlola[0m][.] 61 LTL EXCL 10/619 2/2000 PermAdmissibility-PT-02-LTLCardinality-12 229832 m, 21246 m/sec, 1120308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1132 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 15/2478 3/5 PermAdmissibility-PT-02-LTLCardinality-02 369357 m, 29390 m/sec, 2660018 t fired, .
[[35mlola[0m][.] 61 LTL EXCL 15/619 3/2000 PermAdmissibility-PT-02-LTLCardinality-12 330524 m, 20138 m/sec, 1665934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1137 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 20/2478 4/5 PermAdmissibility-PT-02-LTLCardinality-02 523796 m, 30887 m/sec, 3598193 t fired, .
[[35mlola[0m][.] 61 LTL EXCL 20/619 3/2000 PermAdmissibility-PT-02-LTLCardinality-12 443406 m, 22576 m/sec, 2304853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1142 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 25/2478 5/5 PermAdmissibility-PT-02-LTLCardinality-02 671211 m, 29483 m/sec, 4487255 t fired, .
[[35mlola[0m][.] 61 LTL EXCL 25/619 4/2000 PermAdmissibility-PT-02-LTLCardinality-12 557615 m, 22841 m/sec, 3010862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1147 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 11 (type EXCL) for PermAdmissibility-PT-02-LTLCardinality-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 30/619 5/2000 PermAdmissibility-PT-02-LTLCardinality-12 664577 m, 21392 m/sec, 3608019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1152 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 35/826 6/2000 PermAdmissibility-PT-02-LTLCardinality-12 790222 m, 25129 m/sec, 4380003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1157 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 40/826 6/2000 PermAdmissibility-PT-02-LTLCardinality-12 893981 m, 20751 m/sec, 4963576 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1162 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 45/826 7/2000 PermAdmissibility-PT-02-LTLCardinality-12 1005238 m, 22251 m/sec, 5648795 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1167 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 50/826 8/2000 PermAdmissibility-PT-02-LTLCardinality-12 1102935 m, 19539 m/sec, 6240486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1172 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 55/826 9/2000 PermAdmissibility-PT-02-LTLCardinality-12 1226611 m, 24735 m/sec, 7013739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1177 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 60/826 9/2000 PermAdmissibility-PT-02-LTLCardinality-12 1343174 m, 23312 m/sec, 7741311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1182 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 65/826 10/2000 PermAdmissibility-PT-02-LTLCardinality-12 1455165 m, 22398 m/sec, 8343976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1187 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 70/826 11/2000 PermAdmissibility-PT-02-LTLCardinality-12 1576203 m, 24207 m/sec, 9004076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1192 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 75/826 12/2000 PermAdmissibility-PT-02-LTLCardinality-12 1689198 m, 22599 m/sec, 9640144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1197 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 80/826 12/2000 PermAdmissibility-PT-02-LTLCardinality-12 1804274 m, 23015 m/sec, 10310537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1202 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 85/826 13/2000 PermAdmissibility-PT-02-LTLCardinality-12 1901954 m, 19536 m/sec, 10873658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1207 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 90/826 14/2000 PermAdmissibility-PT-02-LTLCardinality-12 2017219 m, 23053 m/sec, 11552354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1212 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 95/826 14/2000 PermAdmissibility-PT-02-LTLCardinality-12 2122910 m, 21138 m/sec, 12191683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1217 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 100/826 15/2000 PermAdmissibility-PT-02-LTLCardinality-12 2246595 m, 24737 m/sec, 12859257 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1222 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 105/826 16/2000 PermAdmissibility-PT-02-LTLCardinality-12 2359914 m, 22663 m/sec, 13480867 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1227 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 110/826 17/2000 PermAdmissibility-PT-02-LTLCardinality-12 2478125 m, 23642 m/sec, 14174337 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1232 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 115/826 17/2000 PermAdmissibility-PT-02-LTLCardinality-12 2604899 m, 25354 m/sec, 14860141 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1237 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 120/826 18/2000 PermAdmissibility-PT-02-LTLCardinality-12 2720483 m, 23116 m/sec, 15455110 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1242 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 125/826 19/2000 PermAdmissibility-PT-02-LTLCardinality-12 2841847 m, 24272 m/sec, 16123045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1247 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 130/826 20/2000 PermAdmissibility-PT-02-LTLCardinality-12 2954617 m, 22554 m/sec, 16777606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1252 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 135/826 21/2000 PermAdmissibility-PT-02-LTLCardinality-12 3082609 m, 25598 m/sec, 17473254 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1257 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 140/826 21/2000 PermAdmissibility-PT-02-LTLCardinality-12 3202650 m, 24008 m/sec, 18122977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1262 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 145/826 22/2000 PermAdmissibility-PT-02-LTLCardinality-12 3332528 m, 25975 m/sec, 18777014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1267 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 150/826 23/2000 PermAdmissibility-PT-02-LTLCardinality-12 3465660 m, 26626 m/sec, 19421127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1272 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 155/826 24/2000 PermAdmissibility-PT-02-LTLCardinality-12 3597829 m, 26433 m/sec, 20070201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1277 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 160/826 25/2000 PermAdmissibility-PT-02-LTLCardinality-12 3705201 m, 21474 m/sec, 20625645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1282 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 165/826 25/2000 PermAdmissibility-PT-02-LTLCardinality-12 3804882 m, 19936 m/sec, 21163626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1287 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 170/826 26/2000 PermAdmissibility-PT-02-LTLCardinality-12 3916773 m, 22378 m/sec, 21780009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1292 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 175/826 27/2000 PermAdmissibility-PT-02-LTLCardinality-12 4036118 m, 23869 m/sec, 22427741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1297 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 180/826 28/2000 PermAdmissibility-PT-02-LTLCardinality-12 4149801 m, 22736 m/sec, 23080340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1302 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 185/826 28/2000 PermAdmissibility-PT-02-LTLCardinality-12 4278966 m, 25833 m/sec, 23834403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1307 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 190/826 29/2000 PermAdmissibility-PT-02-LTLCardinality-12 4431499 m, 30506 m/sec, 24851140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1312 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 195/826 30/2000 PermAdmissibility-PT-02-LTLCardinality-12 4529391 m, 19578 m/sec, 25382769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1317 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 200/826 31/2000 PermAdmissibility-PT-02-LTLCardinality-12 4634511 m, 21024 m/sec, 25946019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1322 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 205/826 32/2000 PermAdmissibility-PT-02-LTLCardinality-12 4760457 m, 25189 m/sec, 26654824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1327 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 210/826 33/2000 PermAdmissibility-PT-02-LTLCardinality-12 4918539 m, 31616 m/sec, 27626013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1332 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 215/826 33/2000 PermAdmissibility-PT-02-LTLCardinality-12 5037373 m, 23766 m/sec, 28354605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1337 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 220/826 34/2000 PermAdmissibility-PT-02-LTLCardinality-12 5166461 m, 25817 m/sec, 29155957 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1342 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 225/826 35/2000 PermAdmissibility-PT-02-LTLCardinality-12 5279857 m, 22679 m/sec, 29786847 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1347 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 230/826 36/2000 PermAdmissibility-PT-02-LTLCardinality-12 5394138 m, 22856 m/sec, 30446811 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1352 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 235/826 37/2000 PermAdmissibility-PT-02-LTLCardinality-12 5543661 m, 29904 m/sec, 31460942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1357 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 240/826 37/2000 PermAdmissibility-PT-02-LTLCardinality-12 5647500 m, 20767 m/sec, 32027022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1362 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 245/826 38/2000 PermAdmissibility-PT-02-LTLCardinality-12 5762570 m, 23014 m/sec, 32673741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1367 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 250/826 39/2000 PermAdmissibility-PT-02-LTLCardinality-12 5910596 m, 29605 m/sec, 33655143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1372 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 255/826 40/2000 PermAdmissibility-PT-02-LTLCardinality-12 6044972 m, 26875 m/sec, 34513393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1377 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 260/826 41/2000 PermAdmissibility-PT-02-LTLCardinality-12 6164520 m, 23909 m/sec, 35309476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1382 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 265/826 41/2000 PermAdmissibility-PT-02-LTLCardinality-12 6290324 m, 25160 m/sec, 36100419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1387 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 270/826 42/2000 PermAdmissibility-PT-02-LTLCardinality-12 6442504 m, 30436 m/sec, 37013641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1392 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 275/826 43/2000 PermAdmissibility-PT-02-LTLCardinality-12 6573799 m, 26259 m/sec, 37782558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1397 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 280/826 44/2000 PermAdmissibility-PT-02-LTLCardinality-12 6705809 m, 26402 m/sec, 38523209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1402 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 285/826 45/2000 PermAdmissibility-PT-02-LTLCardinality-12 6840842 m, 27006 m/sec, 39321330 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1407 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 290/826 46/2000 PermAdmissibility-PT-02-LTLCardinality-12 6971150 m, 26061 m/sec, 40038409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1412 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 295/826 47/2000 PermAdmissibility-PT-02-LTLCardinality-12 7093876 m, 24545 m/sec, 40755156 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1417 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 300/826 47/2000 PermAdmissibility-PT-02-LTLCardinality-12 7217068 m, 24638 m/sec, 41476556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1422 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 305/826 48/2000 PermAdmissibility-PT-02-LTLCardinality-12 7345990 m, 25784 m/sec, 42250366 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1427 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 310/826 49/2000 PermAdmissibility-PT-02-LTLCardinality-12 7468553 m, 24512 m/sec, 43014532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1432 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 315/826 50/2000 PermAdmissibility-PT-02-LTLCardinality-12 7594493 m, 25188 m/sec, 43808654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1437 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 320/826 51/2000 PermAdmissibility-PT-02-LTLCardinality-12 7701247 m, 21350 m/sec, 44431566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1442 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 325/826 51/2000 PermAdmissibility-PT-02-LTLCardinality-12 7823145 m, 24379 m/sec, 45192396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1447 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 330/826 52/2000 PermAdmissibility-PT-02-LTLCardinality-12 7959553 m, 27281 m/sec, 46048434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1452 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 335/826 53/2000 PermAdmissibility-PT-02-LTLCardinality-12 8077206 m, 23530 m/sec, 46778481 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1457 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 340/826 54/2000 PermAdmissibility-PT-02-LTLCardinality-12 8207434 m, 26045 m/sec, 47638574 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1462 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 345/826 55/2000 PermAdmissibility-PT-02-LTLCardinality-12 8338128 m, 26138 m/sec, 48410790 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1467 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 350/826 56/2000 PermAdmissibility-PT-02-LTLCardinality-12 8469177 m, 26209 m/sec, 49168554 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1472 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 355/826 56/2000 PermAdmissibility-PT-02-LTLCardinality-12 8594012 m, 24967 m/sec, 49846846 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1477 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 LTL EXCL 360/826 57/2000 PermAdmissibility-PT-02-LTLCardinality-12 8721750 m, 25547 m/sec, 50592706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1482 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-07: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-10: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-11: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-PT-02-LTLCardinality-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-14: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-PT-02-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-03: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-PT-02-LTLCardinality-12: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-02"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PermAdmissibility-PT-02, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408300163"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-02.tgz
mv PermAdmissibility-PT-02 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;