About the Execution of LoLA for PermAdmissibility-COL-50
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16206.460 | 1054900.00 | 1978577.00 | 4134.90 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408200146.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PermAdmissibility-COL-50, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408200146
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 6.2K Apr 12 09:06 CTLCardinality.txt
-rw-r--r-- 1 mcc users 63K Apr 12 09:06 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Apr 12 09:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Apr 12 09:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.8K Apr 12 09:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 90K Apr 12 09:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Apr 12 09:13 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Apr 12 09:13 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 54K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-00
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-01
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-02
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-03
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-04
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-05
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-06
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-07
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-08
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-09
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-10
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-11
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-12
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-13
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-14
FORMULA_NAME PermAdmissibility-COL-50-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717088728316
BK_STOP 1717089783216
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Places: 208, Transitions: 1024
[[35mlola[0m][I] Rule S: 432 transitions removed,40 places removed
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 PermAdmissibility-COL-50-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 63 (type FNDP) for 47 PermAdmissibility-COL-50-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 47 PermAdmissibility-COL-50-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type FNDP) for PermAdmissibility-COL-50-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 64 (type EQUN) for PermAdmissibility-COL-50-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 15 PermAdmissibility-COL-50-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 47 PermAdmissibility-COL-50-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for PermAdmissibility-COL-50-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-05: DISJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-13: CONJ 0 1 0 0 4 0 0 2
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 4/199 2/2000 PermAdmissibility-COL-50-CTLFireability-2024-09 274834 m, 54966 m/sec, 2560507 t fired, .
[[35mlola[0m][.] 67 EF STEQ 4/3599 0/5 PermAdmissibility-COL-50-CTLFireability-2024-05 sara not yet started (preprocessing).
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-05: DISJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-13: CONJ 0 1 0 0 4 0 0 2
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 32 CTL EXCL 9/199 3/2000 PermAdmissibility-COL-50-CTLFireability-2024-09 563770 m, 57787 m/sec, 5473169 t fired, .
[[35mlola[0m][.] 67 EF STEQ 9/3599 0/5 PermAdmissibility-COL-50-CTLFireability-2024-05 sara not yet started (preprocessing).
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-05: DISJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-13: CONJ 0 1 0 0 4 0 0 2
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 14/199 4/2000 PermAdmissibility-COL-50-CTLFireability-2024-09 840427 m, 55331 m/sec, 8361244 t fired, .
[[35mlola[0m][.] 67 EF STEQ 14/3599 0/5 PermAdmissibility-COL-50-CTLFireability-2024-05 sara not yet started (preprocessing).
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-05: DISJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-13: CONJ 0 1 0 0 4 0 0 2
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 32 CTL EXCL 19/199 6/2000 PermAdmissibility-COL-50-CTLFireability-2024-09 1093908 m, 50696 m/sec, 11499336 t fired, .
[[35mlola[0m][.] 67 EF STEQ 19/3599 0/5 PermAdmissibility-COL-50-CTLFireability-2024-05 sara not yet started (preprocessing).
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-13: CONJ 0 1 0 0 4 0 0 2
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 24/199 7/2000 PermAdmissibility-COL-50-CTLFireability-2024-09 1335343 m, 48287 m/sec, 14637912 t fired, .
[[35mlola[0m][.] 67 EF STEQ 24/3599 0/5 PermAdmissibility-COL-50-CTLFireability-2024-05 sara not yet started (preprocessing).
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-05: DISJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-13: CONJ 0 1 0 0 4 0 0 2
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-50-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 29/199 8/2000 PermAdmissibility-COL-50-CTLFireability-2024-09 1565207 m, 45972 m/sec, 17680534 t fired, .
[[35mlola[0m][.] 67 EF STEQ 29/3599 0/5 PermAdmissibility-COL-50-CTLFireability-2024-05 sara not yet started (preprocessing).
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[[35mlola[0m][I] FINISHED task # 67 (type EQUN) for PermAdmissibility-COL-50-CTLFireability-2024-05
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[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for PermAdmissibility-COL-50-CTLFireability-2024-13
[[35mlola[0m][I] result : unknown
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-50"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PermAdmissibility-COL-50, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408200146"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-50.tgz
mv PermAdmissibility-COL-50 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;