About the Execution of LoLA for PermAdmissibility-COL-20
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
3929.964 | 31742.00 | 105486.00 | 70.70 | ?TT????T?TT?T?FT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408200139.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PermAdmissibility-COL-20, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408200139
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 552K
-rw-r--r-- 1 mcc users 9.5K Apr 12 09:05 CTLCardinality.txt
-rw-r--r-- 1 mcc users 111K Apr 12 09:05 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Apr 12 09:03 CTLFireability.txt
-rw-r--r-- 1 mcc users 38K Apr 12 09:03 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 12 09:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 133K Apr 12 09:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Apr 12 09:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Apr 12 09:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 54K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-00
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-01
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-02
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-03
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-04
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-05
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-06
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-07
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-08
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-09
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-10
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-11
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-12
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-13
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-14
FORMULA_NAME PermAdmissibility-COL-20-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717088142547
FORMULA PermAdmissibility-COL-20-LTLCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-20-LTLCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-20-LTLCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-20-LTLCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-20-LTLCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-20-LTLCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-20-LTLCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-20-LTLCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717088174289
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Places: 208, Transitions: 1024
[[35mlola[0m][I] findlow criterion satisfied
[[35mlola[0m][I] Time for checking findlow: 2
[[35mlola[0m][I] Rule S: 432 transitions removed,40 places removed
[[35mlola[0m][I] LAUNCH task # 59 (type SKEL/SRCH) for 30 PermAdmissibility-COL-20-LTLCardinality-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 49 (type SKEL/SRCH) for 9 PermAdmissibility-COL-20-LTLCardinality-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 51 (type SKEL/SRCH) for 3 PermAdmissibility-COL-20-LTLCardinality-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH) for 18 PermAdmissibility-COL-20-LTLCardinality-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 59 (type SKEL/SRCH) for PermAdmissibility-COL-20-LTLCardinality-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/EQUN) for 33 PermAdmissibility-COL-20-LTLCardinality-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 51 (type SKEL/SRCH) for PermAdmissibility-COL-20-LTLCardinality-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type SKEL/SRCH) for 6 PermAdmissibility-COL-20-LTLCardinality-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] planning for PermAdmissibility-COL-20-LTLCardinality-01 stopped (result already fixed).
[[35mlola[0m][I] planning for PermAdmissibility-COL-20-LTLCardinality-10 stopped (result already fixed).
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/EQUN) for PermAdmissibility-COL-20-LTLCardinality-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 65 (type SKEL/SRCH) for 33 PermAdmissibility-COL-20-LTLCardinality-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 48 (type SKEL/SRCH) for PermAdmissibility-COL-20-LTLCardinality-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 73584
[[35mlola[0m][I] fired transitions : 263177
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 PermAdmissibility-COL-20-LTLCardinality-15
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for PermAdmissibility-COL-20-LTLCardinality-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 146
[[35mlola[0m][I] fired transitions : 236
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 PermAdmissibility-COL-20-LTLCardinality-14
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for PermAdmissibility-COL-20-LTLCardinality-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 321
[[35mlola[0m][I] fired transitions : 321
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 PermAdmissibility-COL-20-LTLCardinality-13
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-01: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-10: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-COL-20-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-00: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-03: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-04: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-05: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-06: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-07: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-08: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-09: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-11: AU 0 2 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-12: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-13: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 0/326 1/2000 PermAdmissibility-COL-20-LTLCardinality-13 16811 m, 3362 m/sec, 23690 t fired, .
[[35mlola[0m][.] 49 LTL SRCH 0/898 1/5 PermAdmissibility-COL-20-LTLCardinality-03 231433 m, 46286 m/sec, 434451 t fired, .
[[35mlola[0m][.] 60 LTL SRCH 0/898 1/5 PermAdmissibility-COL-20-LTLCardinality-06 110638 m, 22127 m/sec, 637443 t fired, .
[[35mlola[0m][.] 65 ER SRCH 0/898 1/5 PermAdmissibility-COL-20-LTLCardinality-11 193252 m, 38650 m/sec, 363487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-01: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-10: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-COL-20-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-00: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-03: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-04: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-05: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-06: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-07: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-08: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-09: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-11: AU 0 2 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-12: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-13: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 5/326 8/2000 PermAdmissibility-COL-20-LTLCardinality-13 986417 m, 193921 m/sec, 1602946 t fired, .
[[35mlola[0m][.] 49 LTL SRCH 5/898 1/5 PermAdmissibility-COL-20-LTLCardinality-03 2353137 m, 424340 m/sec, 5358724 t fired, .
[[35mlola[0m][.] 60 LTL SRCH 5/898 1/5 PermAdmissibility-COL-20-LTLCardinality-06 1182348 m, 214342 m/sec, 8056759 t fired, .
[[35mlola[0m][.] 65 ER SRCH 5/898 1/5 PermAdmissibility-COL-20-LTLCardinality-11 2511852 m, 463720 m/sec, 6135611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-01: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-10: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-COL-20-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-00: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-03: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-04: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-05: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-06: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-07: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-08: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-09: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-11: AU 0 2 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-12: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-13: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 10/326 15/2000 PermAdmissibility-COL-20-LTLCardinality-13 1899961 m, 182708 m/sec, 3115231 t fired, .
[[35mlola[0m][.] 49 LTL SRCH 10/893 1/5 PermAdmissibility-COL-20-LTLCardinality-03 4337114 m, 396795 m/sec, 9970098 t fired, .
[[35mlola[0m][.] 60 LTL SRCH 10/893 1/5 PermAdmissibility-COL-20-LTLCardinality-06 2216393 m, 206809 m/sec, 15328512 t fired, .
[[35mlola[0m][.] 65 ER SRCH 10/893 1/5 PermAdmissibility-COL-20-LTLCardinality-11 4535445 m, 404718 m/sec, 11582934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-01: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-10: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-COL-20-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-00: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-03: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-04: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-05: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-06: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-07: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-08: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-09: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-11: AU 0 2 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-12: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-13: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 15/326 21/2000 PermAdmissibility-COL-20-LTLCardinality-13 2782755 m, 176558 m/sec, 4637247 t fired, .
[[35mlola[0m][.] 49 LTL SRCH 15/888 1/5 PermAdmissibility-COL-20-LTLCardinality-03 6119741 m, 356525 m/sec, 14299642 t fired, .
[[35mlola[0m][.] 60 LTL SRCH 15/888 1/5 PermAdmissibility-COL-20-LTLCardinality-06 3123975 m, 181516 m/sec, 22489471 t fired, .
[[35mlola[0m][.] 65 ER SRCH 15/888 1/5 PermAdmissibility-COL-20-LTLCardinality-11 6338349 m, 360580 m/sec, 16794907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-01: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-10: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-COL-20-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-00: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-03: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-04: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-05: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-06: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-07: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-08: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-09: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-11: AU 0 2 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-12: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-13: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 20/326 27/2000 PermAdmissibility-COL-20-LTLCardinality-13 3622571 m, 167963 m/sec, 6138594 t fired, .
[[35mlola[0m][.] 49 LTL SRCH 20/883 1/5 PermAdmissibility-COL-20-LTLCardinality-03 7839780 m, 344007 m/sec, 19074143 t fired, .
[[35mlola[0m][.] 60 LTL SRCH 20/883 1/5 PermAdmissibility-COL-20-LTLCardinality-06 4022550 m, 179715 m/sec, 29664902 t fired, .
[[35mlola[0m][.] 65 ER SRCH 20/883 1/5 PermAdmissibility-COL-20-LTLCardinality-11 8429652 m, 418260 m/sec, 21943310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 49 (type SRCH) for PermAdmissibility-COL-20-LTLCardinality-03 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-01: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-10: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-COL-20-LTLCardinality-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-20-LTLCardinality-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-00: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-03: LTL 0 1 0 0 0 0 1 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-04: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-05: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-06: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-07: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-08: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-09: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-11: AU 0 2 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-12: LTL 0 2 0 0 0 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-LTLCardinality-13: LTL 0 1 1 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 25/326 34/2000 PermAdmissibility-COL-20-LTLCardinality-13 4517892 m, 179064 m/sec, 7671957 t fired, .
[[35mlola[0m][.] 60 LTL SRCH 25/878 1/5 PermAdmissibility-COL-20-LTLCardinality-06 4968498 m, 189189 m/sec, 36993702 t fired, .
[[35mlola[0m][.] 65 ER SRCH 25/878 1/5 PermAdmissibility-COL-20-LTLCardinality-11 10036888 m, 321447 m/sec, 27099477 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 50 (type SKEL/SRCH) for 15 PermAdmissibility-COL-20-LTLCardinality-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 50 (type SKEL/SRCH) for PermAdmissibility-COL-20-LTLCardinality-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 556
[[35mlola[0m][I] fired transitions : 559
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 52 (type SKEL/SRCH) for 21 PermAdmissibility-COL-20-LTLCardinality-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type SKEL/SRCH) for PermAdmissibility-COL-20-LTLCardinality-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 53 (type SKEL/SRCH) for 24 PermAdmissibility-COL-20-LTLCardinality-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type SKEL/SRCH) for PermAdmissibility-COL-20-LTLCardinality-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 336
[[35mlola[0m][I] fired transitions : 348
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type SKEL/SRCH) for 27 PermAdmissibility-COL-20-LTLCardinality-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type SKEL/SRCH) for PermAdmissibility-COL-20-LTLCardinality-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/SRCH) for 0 PermAdmissibility-COL-20-LTLCardinality-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type SKEL/SRCH) for PermAdmissibility-COL-20-LTLCardinality-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 322
[[35mlola[0m][I] fired transitions : 322
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 61 (type SKEL/SRCH) for 12 PermAdmissibility-COL-20-LTLCardinality-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type SKEL/SRCH) for PermAdmissibility-COL-20-LTLCardinality-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 321
[[35mlola[0m][I] fired transitions : 321
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type SKEL/SRCH) for 36 PermAdmissibility-COL-20-LTLCardinality-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type SKEL/SRCH) for PermAdmissibility-COL-20-LTLCardinality-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 33 PermAdmissibility-COL-20-LTLCardinality-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Segmentation fault $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-20"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PermAdmissibility-COL-20, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408200139"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-20.tgz
mv PermAdmissibility-COL-20 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;