About the Execution of LoLA for PermAdmissibility-COL-20
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.571 | 2073900.00 | 2310669.00 | 7809.50 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408200138.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PermAdmissibility-COL-20, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408200138
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 552K
-rw-r--r-- 1 mcc users 9.5K Apr 12 09:05 CTLCardinality.txt
-rw-r--r-- 1 mcc users 111K Apr 12 09:05 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Apr 12 09:03 CTLFireability.txt
-rw-r--r-- 1 mcc users 38K Apr 12 09:03 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 12 09:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 133K Apr 12 09:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Apr 12 09:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Apr 12 09:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 54K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-00
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-01
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-02
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-03
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-04
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-05
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-06
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-07
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-08
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-09
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-10
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-11
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-12
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-13
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-14
FORMULA_NAME PermAdmissibility-COL-20-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717088060133
BK_STOP 1717090134033
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Places: 208, Transitions: 1024
[[35mlola[0m][I] Rule S: 432 transitions removed,40 places removed
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 PermAdmissibility-COL-20-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN) for 24 PermAdmissibility-COL-20-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EQUN) for 24 PermAdmissibility-COL-20-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type EQUN) for PermAdmissibility-COL-20-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-08: AGEFAG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 5/211 1/2000 PermAdmissibility-COL-20-CTLFireability-2024-00 65721 m, 13144 m/sec, 108360 t fired, .
[[35mlola[0m][.] 58 EF STEQ 5/3600 0/5 PermAdmissibility-COL-20-CTLFireability-2024-08 sara not yet started (preprocessing).
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[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-08: AGEFAG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 10/211 1/2000 PermAdmissibility-COL-20-CTLFireability-2024-00 124118 m, 11679 m/sec, 203072 t fired, .
[[35mlola[0m][.] 58 EF STEQ 10/3600 0/5 PermAdmissibility-COL-20-CTLFireability-2024-08 sara not yet started (preprocessing).
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[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-08: AGEFAG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 15/211 1/2000 PermAdmissibility-COL-20-CTLFireability-2024-00 171786 m, 9533 m/sec, 282689 t fired, .
[[35mlola[0m][.] 58 EF STEQ 15/3600 0/5 PermAdmissibility-COL-20-CTLFireability-2024-08 sara not yet started (preprocessing).
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[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-08: AGEFAG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 20/211 2/2000 PermAdmissibility-COL-20-CTLFireability-2024-00 220138 m, 9670 m/sec, 365501 t fired, .
[[35mlola[0m][.] 58 EF STEQ 20/3600 0/5 PermAdmissibility-COL-20-CTLFireability-2024-08 sara not yet started (preprocessing).
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[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-08: AGEFAG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 25/211 2/2000 PermAdmissibility-COL-20-CTLFireability-2024-00 267326 m, 9437 m/sec, 453169 t fired, .
[[35mlola[0m][.] 58 EF STEQ 25/3600 0/5 PermAdmissibility-COL-20-CTLFireability-2024-08 sara not yet started (preprocessing).
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[[35mlola[0m][I] FINISHED task # 58 (type EQUN) for PermAdmissibility-COL-20-CTLFireability-2024-08
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-08: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 30/211 2/2000 PermAdmissibility-COL-20-CTLFireability-2024-00 314550 m, 9444 m/sec, 530890 t fired, .
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[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-08: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-20"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PermAdmissibility-COL-20, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408200138"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-20.tgz
mv PermAdmissibility-COL-20 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;