fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r269-smll-171654408200124
Last Updated
July 7, 2024

About the Execution of LoLA for PermAdmissibility-COL-05

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16206.968 271885.00 367947.00 831.40 ?F?F??F?????F??? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408200124.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PermAdmissibility-COL-05, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408200124
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 7.5K Apr 12 09:12 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Apr 12 09:12 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Apr 12 09:09 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Apr 12 09:09 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 23 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 09:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 107K Apr 12 09:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K Apr 12 09:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Apr 12 09:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 54K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-00
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-01
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-02
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-03
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-04
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-05
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-06
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-07
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-08
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-09
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-10
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-11
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-12
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-13
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-14
FORMULA_NAME PermAdmissibility-COL-05-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717086255967

FORMULA PermAdmissibility-COL-05-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717086527852

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains High-Level net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading HL formula in XML format (--xmlformula)
[lola][I] reading formula from LTLFireability.xml
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 68 (type SKEL/CNST) for 13 PermAdmissibility-COL-05-LTLFireability-03
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 68 (type SKEL/CNST) for PermAdmissibility-COL-05-LTLFireability-03
[lola][I] result : false
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 69 (type SKEL/CNST) for 55 PermAdmissibility-COL-05-LTLFireability-13
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 69 (type SKEL/CNST) for PermAdmissibility-COL-05-LTLFireability-13
[lola][I] result : true
[lola][I] Places: 208, Transitions: 1024
[lola][I] Rule S: 432 transitions removed,40 places removed
[lola][I] LAUNCH task # 73 (type EXCL) for 3 PermAdmissibility-COL-05-LTLFireability-01
[lola][I] time limit : 163 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 71 (type FNDP) for 3 PermAdmissibility-COL-05-LTLFireability-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[*** LOG ERROR #0001 ***] [2024-05-30 16:24:16] [status_logger] string pointer is null
[lola][I] LAUNCH task # 72 (type EQUN) for 3 PermAdmissibility-COL-05-LTLFireability-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 73 (type EXCL) for PermAdmissibility-COL-05-LTLFireability-01
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 71 (type FNDP) for PermAdmissibility-COL-05-LTLFireability-01 (obsolete)
[lola][W] CANCELED task # 72 (type EQUN) for PermAdmissibility-COL-05-LTLFireability-01 (obsolete)
[lola][I] LAUNCH task # 44 (type EXCL) for 41 PermAdmissibility-COL-05-LTLFireability-11
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 77 (type FNDP) for 52 PermAdmissibility-COL-05-LTLFireability-12
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 78 (type EQUN) for 52 PermAdmissibility-COL-05-LTLFireability-12
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 82 (type EQUN) for 62 PermAdmissibility-COL-05-LTLFireability-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 44 (type EXCL) for PermAdmissibility-COL-05-LTLFireability-11
[lola][I] result : true
[lola][I] markings : 30
[lola][I] fired transitions : 36
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 66 (type EXCL) for 65 PermAdmissibility-COL-05-LTLFireability-15
[lola][I] time limit : 200 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 71 (type FNDP) for PermAdmissibility-COL-05-LTLFireability-01
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 77 (type FNDP) for PermAdmissibility-COL-05-LTLFireability-12
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 78 (type EQUN) for PermAdmissibility-COL-05-LTLFireability-12 (obsolete)
[lola][I] LAUNCH task # 84 (type FNDP) for 26 PermAdmissibility-COL-05-LTLFireability-06
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 85 (type EQUN) for 26 PermAdmissibility-COL-05-LTLFireability-06
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 84 (type FNDP) for PermAdmissibility-COL-05-LTLFireability-06
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 85 (type EQUN) for PermAdmissibility-COL-05-LTLFireability-06 (obsolete)
[lola][I] FINISHED task # 82 (type EQUN) for PermAdmissibility-COL-05-LTLFireability-14
[lola][I] result : true
[lola][I] findlow criterion satisfied
[lola][I] Time for checking findlow: 1
[lola][I] LAUNCH task # 87 (type SKEL/SRCH) for 32 PermAdmissibility-COL-05-LTLFireability-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 88 (type SKEL/SRCH) for 41 PermAdmissibility-COL-05-LTLFireability-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 91 (type SKEL/SRCH) for 41 PermAdmissibility-COL-05-LTLFireability-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 88 (type SKEL/SRCH) for PermAdmissibility-COL-05-LTLFireability-11
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] FINISHED task # 91 (type SKEL/SRCH) for PermAdmissibility-COL-05-LTLFireability-11
[lola][I] result : true
[lola][I] markings : 4
[lola][I] fired transitions : 3
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] FINISHED task # 87 (type SKEL/SRCH) for PermAdmissibility-COL-05-LTLFireability-08
[lola][I] result : true
[lola][I] markings : 36964
[lola][I] fired transitions : 130100
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] PermAdmissibility-COL-05-LTLFireability-01: CONJ false state space
[lola][.] PermAdmissibility-COL-05-LTLFireability-03: CONJ false skeleton: preprocessing
[lola][.] PermAdmissibility-COL-05-LTLFireability-06: AG false findpath
[lola][.] PermAdmissibility-COL-05-LTLFireability-08: LTL true skeleton: LTL model checker
[lola][.] PermAdmissibility-COL-05-LTLFireability-11: CONJ true CONJ
[lola][.] PermAdmissibility-COL-05-LTLFireability-12: AG false findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] PermAdmissibility-COL-05-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-14: F 0 1 0 0 2 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 66 LTL EXCL 5/360 4/2000 PermAdmissibility-COL-05-LTLFireability-15 496941 m, 99388 m/sec, 533284 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 4
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] PermAdmissibility-COL-05-LTLFireability-01: CONJ false state space
[lola][.] PermAdmissibility-COL-05-LTLFireability-03: CONJ false skeleton: preprocessing
[lola][.] PermAdmissibility-COL-05-LTLFireability-06: AG false findpath
[lola][.] PermAdmissibility-COL-05-LTLFireability-08: LTL true skeleton: LTL model checker
[lola][.] PermAdmissibility-COL-05-LTLFireability-11: CONJ true CONJ
[lola][.] PermAdmissibility-COL-05-LTLFireability-12: AG false findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] PermAdmissibility-COL-05-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-14: F 0 1 0 0 2 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 66 LTL EXCL 10/360 9/2000 PermAdmissibility-COL-05-LTLFireability-15 1270244 m, 154660 m/sec, 1379454 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 9
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] PermAdmissibility-COL-05-LTLFireability-01: CONJ false state space
[lola][.] PermAdmissibility-COL-05-LTLFireability-03: CONJ false skeleton: preprocessing
[lola][.] PermAdmissibility-COL-05-LTLFireability-06: AG false findpath
[lola][.] PermAdmissibility-COL-05-LTLFireability-08: LTL true skeleton: LTL model checker
[lola][.] PermAdmissibility-COL-05-LTLFireability-11: CONJ true CONJ
[lola][.] PermAdmissibility-COL-05-LTLFireability-12: AG false findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] PermAdmissibility-COL-05-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-14: F 0 1 0 0 2 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 66 LTL EXCL 15/360 14/2000 PermAdmissibility-COL-05-LTLFireability-15 2040888 m, 154128 m/sec, 2230811 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 14
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] PermAdmissibility-COL-05-LTLFireability-01: CONJ false state space
[lola][.] PermAdmissibility-COL-05-LTLFireability-03: CONJ false skeleton: preprocessing
[lola][.] PermAdmissibility-COL-05-LTLFireability-06: AG false findpath
[lola][.] PermAdmissibility-COL-05-LTLFireability-08: LTL true skeleton: LTL model checker
[lola][.] PermAdmissibility-COL-05-LTLFireability-11: CONJ true CONJ
[lola][.] PermAdmissibility-COL-05-LTLFireability-12: AG false findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] PermAdmissibility-COL-05-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-14: F 0 1 0 0 2 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 66 LTL EXCL 20/360 18/2000 PermAdmissibility-COL-05-LTLFireability-15 2709201 m, 133662 m/sec, 2970352 t fired, .
[lola][.]
[lola][.] Time elapsed: 20 secs. Pages in use: 18
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] PermAdmissibility-COL-05-LTLFireability-01: CONJ false state space
[lola][.] PermAdmissibility-COL-05-LTLFireability-03: CONJ false skeleton: preprocessing
[lola][.] PermAdmissibility-COL-05-LTLFireability-06: AG false findpath
[lola][.] PermAdmissibility-COL-05-LTLFireability-08: LTL true skeleton: LTL model checker
[lola][.] PermAdmissibility-COL-05-LTLFireability-11: CONJ true CONJ
[lola][.] PermAdmissibility-COL-05-LTLFireability-12: AG false findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] PermAdmissibility-COL-05-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-14: F 0 1 0 0 2 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 66 LTL EXCL 25/360 23/2000 PermAdmissibility-COL-05-LTLFireability-15 3494136 m, 156987 m/sec, 3839518 t fired, .
[lola][.]
[lola][.] Time elapsed: 25 secs. Pages in use: 23
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] PermAdmissibility-COL-05-LTLFireability-01: CONJ false state space
[lola][.] PermAdmissibility-COL-05-LTLFireability-03: CONJ false skeleton: preprocessing
[lola][.] PermAdmissibility-COL-05-LTLFireability-06: AG false findpath
[lola][.] PermAdmissibility-COL-05-LTLFireability-08: LTL true skeleton: LTL model checker
[lola][.] PermAdmissibility-COL-05-LTLFireability-11: CONJ true CONJ
[lola][.] PermAdmissibility-COL-05-LTLFireability-12: AG false findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] PermAdmissibility-COL-05-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-14: F 0 1 0 0 2 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 66 LTL EXCL 30/360 28/2000 PermAdmissibility-COL-05-LTLFireability-15 4263718 m, 153916 m/sec, 4708648 t fired, .
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[lola][.] 66 LTL EXCL 35/360 34/2000 PermAdmissibility-COL-05-LTLFireability-15 5083105 m, 163877 m/sec, 5634306 t fired, .
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[lola][.] 66 LTL EXCL 40/360 39/2000 PermAdmissibility-COL-05-LTLFireability-15 5937471 m, 170873 m/sec, 6616827 t fired, .
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[lola][.] 66 LTL EXCL 45/360 45/2000 PermAdmissibility-COL-05-LTLFireability-15 6768414 m, 166188 m/sec, 7599141 t fired, .
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[lola][.] 66 LTL EXCL 50/360 50/2000 PermAdmissibility-COL-05-LTLFireability-15 7612603 m, 168837 m/sec, 8541256 t fired, .
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[lola][.] 66 LTL EXCL 55/360 56/2000 PermAdmissibility-COL-05-LTLFireability-15 8454691 m, 168417 m/sec, 9482657 t fired, .
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[lola][.] 66 LTL EXCL 60/360 61/2000 PermAdmissibility-COL-05-LTLFireability-15 9297124 m, 168486 m/sec, 10432659 t fired, .
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[lola][.] 66 LTL EXCL 65/360 67/2000 PermAdmissibility-COL-05-LTLFireability-15 10138936 m, 168362 m/sec, 11382965 t fired, .
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[lola][.] 66 LTL EXCL 70/360 72/2000 PermAdmissibility-COL-05-LTLFireability-15 10963947 m, 165002 m/sec, 12317279 t fired, .
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[lola][.] 66 LTL EXCL 75/360 77/2000 PermAdmissibility-COL-05-LTLFireability-15 11761822 m, 159575 m/sec, 13238509 t fired, .
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[lola][.] 66 LTL EXCL 80/360 83/2000 PermAdmissibility-COL-05-LTLFireability-15 12596028 m, 166841 m/sec, 14203386 t fired, .
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[lola][.] 66 LTL EXCL 85/360 88/2000 PermAdmissibility-COL-05-LTLFireability-15 13430842 m, 166962 m/sec, 15186893 t fired, .
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[lola][.] 66 LTL EXCL 90/360 94/2000 PermAdmissibility-COL-05-LTLFireability-15 14254913 m, 164814 m/sec, 16172490 t fired, .
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[lola][.] 66 LTL EXCL 95/360 99/2000 PermAdmissibility-COL-05-LTLFireability-15 15081883 m, 165394 m/sec, 17181396 t fired, .
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[lola][.] 66 LTL EXCL 100/360 105/2000 PermAdmissibility-COL-05-LTLFireability-15 15911456 m, 165914 m/sec, 18163490 t fired, .
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[lola][.] 66 LTL EXCL 105/360 110/2000 PermAdmissibility-COL-05-LTLFireability-15 16726195 m, 162947 m/sec, 19135777 t fired, .
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[lola][.] 66 LTL EXCL 110/360 115/2000 PermAdmissibility-COL-05-LTLFireability-15 17542528 m, 163266 m/sec, 20115738 t fired, .
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[lola][.] 66 LTL EXCL 115/360 121/2000 PermAdmissibility-COL-05-LTLFireability-15 18352535 m, 162001 m/sec, 21109760 t fired, .
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[lola][.] 66 LTL EXCL 120/360 126/2000 PermAdmissibility-COL-05-LTLFireability-15 19157560 m, 161005 m/sec, 22102919 t fired, .
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[lola][.] 66 LTL EXCL 125/360 131/2000 PermAdmissibility-COL-05-LTLFireability-15 19952905 m, 159069 m/sec, 23086531 t fired, .
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[lola][.] 66 LTL EXCL 130/360 136/2000 PermAdmissibility-COL-05-LTLFireability-15 20750578 m, 159534 m/sec, 24067626 t fired, .
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[lola][.] 66 LTL EXCL 135/360 141/2000 PermAdmissibility-COL-05-LTLFireability-15 21538496 m, 157583 m/sec, 25052521 t fired, .
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[lola][.] 66 LTL EXCL 140/360 147/2000 PermAdmissibility-COL-05-LTLFireability-15 22332086 m, 158718 m/sec, 26059889 t fired, .
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[lola][.] 66 LTL EXCL 145/360 152/2000 PermAdmissibility-COL-05-LTLFireability-15 23181044 m, 169791 m/sec, 26998990 t fired, .
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[lola][.] 66 LTL EXCL 150/360 157/2000 PermAdmissibility-COL-05-LTLFireability-15 23959091 m, 155609 m/sec, 27879876 t fired, .
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[lola][.] 66 LTL EXCL 155/360 163/2000 PermAdmissibility-COL-05-LTLFireability-15 24794141 m, 167010 m/sec, 28829669 t fired, .
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[lola][.] 66 LTL EXCL 160/360 168/2000 PermAdmissibility-COL-05-LTLFireability-15 25591781 m, 159528 m/sec, 29752429 t fired, .
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[lola][.] 66 LTL EXCL 165/360 173/2000 PermAdmissibility-COL-05-LTLFireability-15 26319315 m, 145506 m/sec, 30618129 t fired, .
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[lola][.] 66 LTL EXCL 170/360 178/2000 PermAdmissibility-COL-05-LTLFireability-15 27162716 m, 168680 m/sec, 31610977 t fired, .
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[lola][.] 66 LTL EXCL 175/360 184/2000 PermAdmissibility-COL-05-LTLFireability-15 27992745 m, 166005 m/sec, 32562306 t fired, .
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[lola][.] 66 LTL EXCL 180/360 189/2000 PermAdmissibility-COL-05-LTLFireability-15 28830246 m, 167500 m/sec, 33539886 t fired, .
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[lola][.] 66 LTL EXCL 185/360 194/2000 PermAdmissibility-COL-05-LTLFireability-15 29660964 m, 166143 m/sec, 34517968 t fired, .
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[lola][.] 66 LTL EXCL 190/360 200/2000 PermAdmissibility-COL-05-LTLFireability-15 30475709 m, 162949 m/sec, 35494058 t fired, .
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[lola][.] 66 LTL EXCL 195/360 205/2000 PermAdmissibility-COL-05-LTLFireability-15 31291471 m, 163152 m/sec, 36504453 t fired, .
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[lola][.] 66 LTL EXCL 200/360 211/2000 PermAdmissibility-COL-05-LTLFireability-15 32109065 m, 163518 m/sec, 37527704 t fired, .
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[lola][.] 66 LTL EXCL 205/360 216/2000 PermAdmissibility-COL-05-LTLFireability-15 32914610 m, 161109 m/sec, 38528727 t fired, .
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[lola][.] 66 LTL EXCL 210/360 221/2000 PermAdmissibility-COL-05-LTLFireability-15 33735688 m, 164215 m/sec, 39570704 t fired, .
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[lola][.] 66 LTL EXCL 215/360 226/2000 PermAdmissibility-COL-05-LTLFireability-15 34552342 m, 163330 m/sec, 40627904 t fired, .
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[lola][.] 66 LTL EXCL 220/360 232/2000 PermAdmissibility-COL-05-LTLFireability-15 35371016 m, 163734 m/sec, 41678165 t fired, .
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[lola][.] 66 LTL EXCL 225/360 237/2000 PermAdmissibility-COL-05-LTLFireability-15 36183502 m, 162497 m/sec, 42756353 t fired, .
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[lola][.] 66 LTL EXCL 230/360 243/2000 PermAdmissibility-COL-05-LTLFireability-15 37075687 m, 178437 m/sec, 43814896 t fired, .
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[lola][.] 66 LTL EXCL 235/360 249/2000 PermAdmissibility-COL-05-LTLFireability-15 37943605 m, 173583 m/sec, 44870500 t fired, .
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[lola][.] 66 LTL EXCL 240/360 254/2000 PermAdmissibility-COL-05-LTLFireability-15 38759824 m, 163243 m/sec, 45912083 t fired, .
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[lola][.] 66 LTL EXCL 245/360 259/2000 PermAdmissibility-COL-05-LTLFireability-15 39589673 m, 165969 m/sec, 47020772 t fired, .
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[lola][.] 66 LTL EXCL 250/360 265/2000 PermAdmissibility-COL-05-LTLFireability-15 40412977 m, 164660 m/sec, 47993158 t fired, .
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[lola][.] 66 LTL EXCL 255/360 270/2000 PermAdmissibility-COL-05-LTLFireability-15 41243789 m, 166162 m/sec, 48904178 t fired, .
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[lola][.] PermAdmissibility-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-14: F 0 1 0 0 2 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 66 LTL EXCL 265/360 281/2000 PermAdmissibility-COL-05-LTLFireability-15 42916927 m, 167016 m/sec, 50757953 t fired, .
[lola][.]
[lola][.] Time elapsed: 265 secs. Pages in use: 281
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] PermAdmissibility-COL-05-LTLFireability-01: CONJ false state space
[lola][.] PermAdmissibility-COL-05-LTLFireability-03: CONJ false skeleton: preprocessing
[lola][.] PermAdmissibility-COL-05-LTLFireability-06: AG false findpath
[lola][.] PermAdmissibility-COL-05-LTLFireability-08: LTL true skeleton: LTL model checker
[lola][.] PermAdmissibility-COL-05-LTLFireability-11: CONJ true CONJ
[lola][.] PermAdmissibility-COL-05-LTLFireability-12: AG false findpath
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] PermAdmissibility-COL-05-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-14: F 0 1 0 0 2 0 0 0
[lola][.] PermAdmissibility-COL-05-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 66 LTL EXCL 270/360 286/2000 PermAdmissibility-COL-05-LTLFireability-15 43674407 m, 151496 m/sec, 51598324 t fired, .
[lola][.]
[lola][.] Time elapsed: 270 secs. Pages in use: 286
[lola][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-05"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PermAdmissibility-COL-05, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408200124"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-05.tgz
mv PermAdmissibility-COL-05 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;