About the Execution of LoLA for PermAdmissibility-COL-05
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.455 | 1612200.00 | 2580863.00 | 8509.80 | ?????????????FT? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408200122.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PermAdmissibility-COL-05, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408200122
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 7.5K Apr 12 09:12 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Apr 12 09:12 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Apr 12 09:09 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Apr 12 09:09 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 23 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 23 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 09:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 107K Apr 12 09:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K Apr 12 09:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Apr 12 09:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 54K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-00
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-01
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-02
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-03
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-04
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-05
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-06
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-07
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-08
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-09
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-10
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-11
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-12
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-13
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-14
FORMULA_NAME PermAdmissibility-COL-05-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717082804214
FORMULA PermAdmissibility-COL-05-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717084416414
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/FNDP) for 58 PermAdmissibility-COL-05-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type SKEL/EQUN) for 58 PermAdmissibility-COL-05-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 71 (type SKEL/SRCH) for 58 PermAdmissibility-COL-05-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] Places: 208, Transitions: 1024
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/FNDP) for PermAdmissibility-COL-05-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 70 (type EQUN) for PermAdmissibility-COL-05-CTLFireability-2024-14 (obsolete)
[[35mlola[0m][W] CANCELED task # 71 (type SRCH) for PermAdmissibility-COL-05-CTLFireability-2024-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 74 (type SKEL/FNDP) for 51 PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 75 (type SKEL/EQUN) for 51 PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type SKEL/SRCH) for 51 PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 76 (type SKEL/SRCH) for PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 74 (type FNDP) for PermAdmissibility-COL-05-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][W] CANCELED task # 75 (type EQUN) for PermAdmissibility-COL-05-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][I] FINISHED task # 74 (type SKEL/FNDP) for PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 75 (type SKEL/EQUN) for PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 70 (type SKEL/EQUN) for PermAdmissibility-COL-05-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 432 transitions removed,40 places removed
[[35mlola[0m][I] LAUNCH task # 80 (type EXCL) for 51 PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 78 (type FNDP) for 51 PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 79 (type EQUN) for 51 PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 78 (type FNDP) for PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 79 (type EQUN) for PermAdmissibility-COL-05-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][W] CANCELED task # 80 (type EXCL) for PermAdmissibility-COL-05-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][I] LAUNCH task # 9 (type EXCL) for 6 PermAdmissibility-COL-05-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 79 (type EQUN) for PermAdmissibility-COL-05-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 92 (type FNDP) for 58 PermAdmissibility-COL-05-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 93 (type EQUN) for 58 PermAdmissibility-COL-05-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 101 (type EQUN) for 19 PermAdmissibility-COL-05-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 92 (type FNDP) for PermAdmissibility-COL-05-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 93 (type EQUN) for PermAdmissibility-COL-05-CTLFireability-2024-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 86 (type EQUN) for 65 PermAdmissibility-COL-05-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 98 (type EQUN) for 65 PermAdmissibility-COL-05-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 86 (type EQUN) for PermAdmissibility-COL-05-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 103 (type EQUN) for 19 PermAdmissibility-COL-05-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 103 (type EQUN) for PermAdmissibility-COL-05-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] findlow criterion satisfied
[[35mlola[0m][I] Time for checking findlow: 2
[[35mlola[0m][I] FINISHED task # 93 (type EQUN) for PermAdmissibility-COL-05-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-COL-05-CTLFireability-2024-13: CONJ false findpath[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-05-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-05: CONJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-15: AGAF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 CTL EXCL 4/211 1/2000 PermAdmissibility-COL-05-CTLFireability-2024-02 179674 m, 35934 m/sec, 2454559 t fired, .
[[35mlola[0m][.] 98 EF STEQ 4/3599 0/5 PermAdmissibility-COL-05-CTLFireability-2024-15 sara not yet started (preprocessing).
[[35mlola[0m][.] 101 EF STEQ 4/3599 0/5 PermAdmissibility-COL-05-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-COL-05-CTLFireability-2024-13: CONJ false findpath[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-05-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-05: CONJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-15: AGAF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 CTL EXCL 9/211 2/2000 PermAdmissibility-COL-05-CTLFireability-2024-02 371716 m, 38408 m/sec, 5428151 t fired, .
[[35mlola[0m][.] 98 EF STEQ 9/3599 0/5 PermAdmissibility-COL-05-CTLFireability-2024-15 sara not yet started (preprocessing).
[[35mlola[0m][.] 101 EF STEQ 9/3599 0/5 PermAdmissibility-COL-05-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-COL-05-CTLFireability-2024-13: CONJ false findpath[0m
[[35mlola[0m][.] [1m[32mPermAdmissibility-COL-05-CTLFireability-2024-14: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-02: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-05: CONJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PermAdmissibility-COL-05-CTLFireability-2024-15: AGAF 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 9 CTL EXCL 14/211 3/2000 PermAdmissibility-COL-05-CTLFireability-2024-02 565729 m, 38802 m/sec, 8909757 t fired, .
[[35mlola[0m][.] 98 EF STEQ 14/3599 0/5 PermAdmissibility-COL-05-CTLFireability-2024-15 sara not yet started (preprocessing).
[[35mlola[0m][.] 101 EF STEQ 14/3599 0/5 PermAdmissibility-COL-05-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPermAdmissibility-COL-05-CTLFireability-2024-13: CONJ false findpath[0m
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-05"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PermAdmissibility-COL-05, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408200122"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-05.tgz
mv PermAdmissibility-COL-05 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;