MCC'2024- Execution of r269-smll-171654408000052

About the Execution of LoLA for ParamProductionCell-PT-5

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
1123.792	61071.00	111592.00	262.40	FFFTFFFTFTTTFFFF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408000052.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ParamProductionCell-PT-5, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408000052
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 608K
-rw-r--r-- 1 mcc users 7.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 60K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.6K Apr 23 07:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 23 07:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Apr 23 07:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 12 20:33 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 125K Apr 12 20:33 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.8K Apr 12 20:31 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 48K Apr 12 20:31 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 07:41 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:41 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 2 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 174K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-00
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-01
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-02
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-03
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-04
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-05
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-06
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-07
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-08
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-09
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-10
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-11
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-12
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-13
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-14
FORMULA_NAME ParamProductionCell-PT-5-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717055431948

FORMULA ParamProductionCell-PT-5-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-5-LTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-5-LTLFireability-03: F true state space / EG[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-05: CONJ false preprocessing[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-06: LTL/CTL false LTL model checker[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-5-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-5-LTLFireability-09: LTL true LTL model checker[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-5-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-5-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-5-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 60 secs. Pages in use: 33

BK_STOP 1717055493019

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 32 ParamProductionCell-PT-5-LTLFireability-08
[[35mlola[0m][I] time limit : 112 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 267
[[35mlola[0m][I] fired transitions : 268
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 19 ParamProductionCell-PT-5-LTLFireability-05
[[35mlola[0m][I] time limit : 124 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 24 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 ParamProductionCell-PT-5-LTLFireability-06
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[*** LOG ERROR #0001 ***] [2024-05-30 07:50:36] [status_logger] string pointer is null
[[35mlola[0m][I] FINISHED task # 27 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 280
[[35mlola[0m][I] fired transitions : 280
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 73 (type EXCL) for 48 ParamProductionCell-PT-5-LTLFireability-12
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 76 (type EQUN) for 48 ParamProductionCell-PT-5-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 22 (type CNST) for 19 ParamProductionCell-PT-5-LTLFireability-05
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 22 (type CNST) for ParamProductionCell-PT-5-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 81 (type EQUN) for 13 ParamProductionCell-PT-5-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 83 (type FNDP) for 48 ParamProductionCell-PT-5-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 83 (type FNDP) for ParamProductionCell-PT-5-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 73 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-12 (obsolete)
[[35mlola[0m][W] CANCELED task # 76 (type EQUN) for ParamProductionCell-PT-5-LTLFireability-12 (obsolete)
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 66 ParamProductionCell-PT-5-LTLFireability-14
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 387
[[35mlola[0m][I] fired transitions : 387
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 59 ParamProductionCell-PT-5-LTLFireability-13
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 280
[[35mlola[0m][I] fired transitions : 280
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 ParamProductionCell-PT-5-LTLFireability-11
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 89 (type EQUN) for 0 ParamProductionCell-PT-5-LTLFireability-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-05: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-06: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-00: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-03: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 5/326 7/2000 ParamProductionCell-PT-5-LTLFireability-11 878120 m, 175624 m/sec, 3445469 t fired, .
[[35mlola[0m][.] 81 EF STEQ 5/3596 0/5 ParamProductionCell-PT-5-LTLFireability-03 sara not yet started (preprocessing).
[[35mlola[0m][.] 89 EF STEQ 5/3596 0/5 ParamProductionCell-PT-5-LTLFireability-00 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 9 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 76 (type EQUN) for ParamProductionCell-PT-5-LTLFireability-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-05: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-06: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-00: CONJ 0 2 1 0 2 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-03: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-5-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 10/326 10/2000 ParamProductionCell-PT-5-LTLFireability-11 1454061 m, 115188 m/sec, 7380517 t fired, .
[[35mlola[0m][.] 81 EF STEQ 10/3596 0/5 ParamProductionCell-PT-5-LTLFireability-03 sara not yet started (preprocessing).
[[35mlola[0m][.] 89 EF STEQ 10/3596 0/5 ParamProductionCell-PT-5-LTLFireability-00 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 14 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 89 (type EQUN) for ParamProductionCell-PT-5-LTLFireability-00
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-05: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-06: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-5-LTLFireability-14: LTL false LTL model checker[0m
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[[35mlola[0m][I] fired transitions : 10373115
[[35mlola[0m][I] time used : 15
[[35mlola[0m][I] memory pages used : 17
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 ParamProductionCell-PT-5-LTLFireability-07
[[35mlola[0m][I] time limit : 393 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 62432
[[35mlola[0m][I] fired transitions : 232200
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 5 (type EXCL) for 0 ParamProductionCell-PT-5-LTLFireability-00
[[35mlola[0m][I] time limit : 442 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 5 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 280
[[35mlola[0m][I] fired transitions : 280
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 78 (type EXCL) for 13 ParamProductionCell-PT-5-LTLFireability-03
[[35mlola[0m][I] time limit : 590 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 78 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 70 (type EXCL) for 69 ParamProductionCell-PT-5-LTLFireability-15
[[35mlola[0m][I] time limit : 708 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 308
[[35mlola[0m][I] fired transitions : 309
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 ParamProductionCell-PT-5-LTLFireability-01
[[35mlola[0m][I] time limit : 885 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1769
[[35mlola[0m][I] fired transitions : 1922
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 ParamProductionCell-PT-5-LTLFireability-04
[[35mlola[0m][I] time limit : 1180 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3418
[[35mlola[0m][I] fired transitions : 3703
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 ParamProductionCell-PT-5-LTLFireability-02
[[35mlola[0m][I] time limit : 1770 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 239
[[35mlola[0m][I] fired transitions : 239
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 ParamProductionCell-PT-5-LTLFireability-09
[[35mlola[0m][I] time limit : 3540 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for ParamProductionCell-PT-5-LTLFireability-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 85977
[[35mlola[0m][I] fired transitions : 110611
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-5"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ParamProductionCell-PT-5, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408000052"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-5.tgz
mv ParamProductionCell-PT-5 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;