Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408000042.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ParamProductionCell-PT-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408000042
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 684K
-rw-r--r-- 1 mcc users 8.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Apr 23 07:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 07:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Apr 23 07:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 23 07:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Apr 12 20:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 161K Apr 12 20:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Apr 12 20:30 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 55K Apr 12 20:30 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 07:41 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:41 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 2 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 174K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-00
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-01
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-02
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-03
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-04
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-05
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-06
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-07
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-08
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-09
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-10
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2024-11
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2023-12
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2023-13
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2023-14
FORMULA_NAME ParamProductionCell-PT-4-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717054451948

FORMULA ParamProductionCell-PT-4-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2023-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-4-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] ParamProductionCell-PT-4-CTLFireability-2024-00: CTL true CTL model checker
[lola] ParamProductionCell-PT-4-CTLFireability-2024-01: CTL true CTL model checker
[lola] ParamProductionCell-PT-4-CTLFireability-2024-02: CTL true CTL model checker
[lola] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF true CTL model checker
[lola] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL true CTL model checker
[lola] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ true CONJ
[lola] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola] ParamProductionCell-PT-4-CTLFireability-2023-13: CTL true CTL model checker
[lola] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola]
[lola] Time elapsed: 66 secs. Pages in use: 12

BK_STOP 1717054518564

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 28 (type CNST) for 27 ParamProductionCell-PT-4-CTLFireability-2024-09
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 28 (type CNST) for ParamProductionCell-PT-4-CTLFireability-2024-09
[lola][I] result : true
[lola][I] LAUNCH task # 31 (type CNST) for 30 ParamProductionCell-PT-4-CTLFireability-2024-10
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 31 (type CNST) for ParamProductionCell-PT-4-CTLFireability-2024-10
[lola][I] result : false
[lola][I] LAUNCH task # 58 (type EXCL) for 12 ParamProductionCell-PT-4-CTLFireability-2024-04
[lola][I] time limit : 170 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 56 (type FNDP) for 12 ParamProductionCell-PT-4-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 57 (type EQUN) for 12 ParamProductionCell-PT-4-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 56 (type FNDP) for ParamProductionCell-PT-4-CTLFireability-2024-04
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 57 (type EQUN) for ParamProductionCell-PT-4-CTLFireability-2024-04 (obsolete)
[lola][W] CANCELED task # 58 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-04 (obsolete)
[lola][I] LAUNCH task # 25 (type EXCL) for 24 ParamProductionCell-PT-4-CTLFireability-2024-08
[lola][I] time limit : 179 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 25 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-08
[lola][I] result : true
[lola][I] markings : 395
[lola][I] fired transitions : 1182
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 45 (type EXCL) for 44 ParamProductionCell-PT-4-CTLFireability-2023-12
[lola][I] time limit : 199 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 59 (type FNDP) for 50 ParamProductionCell-PT-4-CTLFireability-2023-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 60 (type EQUN) for 50 ParamProductionCell-PT-4-CTLFireability-2023-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 59 (type FNDP) for ParamProductionCell-PT-4-CTLFireability-2023-14
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 60 (type EQUN) for ParamProductionCell-PT-4-CTLFireability-2023-14 (obsolete)
[lola][I] LAUNCH task # 65 (type EQUN) for 33 ParamProductionCell-PT-4-CTLFireability-2024-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 69 (type EQUN) for 33 ParamProductionCell-PT-4-CTLFireability-2024-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 65 (type EQUN) for ParamProductionCell-PT-4-CTLFireability-2024-11
[lola][I] result : unknown
[lola][I] FINISHED task # 57 (type EQUN) for ParamProductionCell-PT-4-CTLFireability-2024-04
[lola][I] result : unknown
[lola][I] FINISHED task # 45 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2023-12
[lola][I] result : false
[lola][I] markings : 62768
[lola][I] fired transitions : 201611
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 66 (type EXCL) for 33 ParamProductionCell-PT-4-CTLFireability-2024-11
[lola][I] time limit : 298 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 66 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-11
[lola][I] result : true
[lola][I] markings : 294
[lola][I] fired transitions : 294
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 69 (type EQUN) for ParamProductionCell-PT-4-CTLFireability-2024-11 (obsolete)
[lola][I] LAUNCH task # 54 (type EXCL) for 53 ParamProductionCell-PT-4-CTLFireability-2023-15
[lola][I] time limit : 358 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 54 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2023-15
[lola][I] result : false
[lola][I] markings : 207
[lola][I] fired transitions : 300
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 22 (type EXCL) for 21 ParamProductionCell-PT-4-CTLFireability-2024-07
[lola][I] time limit : 398 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 69 (type EQUN) for ParamProductionCell-PT-4-CTLFireability-2024-11
[lola][I] result : unknown
[lola][I] FINISHED task # 22 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-07
[lola][I] result : true
[lola][I] markings : 611643
[lola][I] fired transitions : 2368866
[lola][I] time used : 4
[lola][I] memory pages used : 3
[lola][I] LAUNCH task # 19 (type EXCL) for 18 ParamProductionCell-PT-4-CTLFireability-2024-06
[lola][I] time limit : 447 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 19 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-06
[lola][I] result : true
[lola][I] markings : 5888
[lola][I] fired transitions : 10860
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 16 (type EXCL) for 15 ParamProductionCell-PT-4-CTLFireability-2024-05
[lola][I] time limit : 511 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ 0 1 0 0 6 0 0 1
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 16 CTL EXCL 1/511 1/2000 ParamProductionCell-PT-4-CTLFireability-2024-05 44337 m, 8867 m/sec, 133522 t fired, .
[lola][.]
[lola][.] Time elapsed: 18 secs. Pages in use: 3
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 16 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-05
[lola][I] result : true
[lola][I] markings : 260886
[lola][I] fired transitions : 960853
[lola][I] time used : 2
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 7 (type EXCL) for 6 ParamProductionCell-PT-4-CTLFireability-2024-02
[lola][I] time limit : 596 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 7 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-02
[lola][I] result : true
[lola][I] markings : 400776
[lola][I] fired transitions : 1480113
[lola][I] time used : 2
[lola][I] memory pages used : 2
[lola][I] LAUNCH task # 4 (type EXCL) for 3 ParamProductionCell-PT-4-CTLFireability-2024-01
[lola][I] time limit : 715 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ 0 1 0 0 6 0 0 1
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 CTL EXCL 2/715 2/2000 ParamProductionCell-PT-4-CTLFireability-2024-01 365825 m, 73165 m/sec, 1079757 t fired, .
[lola][.]
[lola][.] Time elapsed: 23 secs. Pages in use: 3
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ 0 1 0 0 6 0 0 1
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 CTL EXCL 7/715 6/2000 ParamProductionCell-PT-4-CTLFireability-2024-01 1218645 m, 170564 m/sec, 4121083 t fired, .
[lola][.]
[lola][.] Time elapsed: 28 secs. Pages in use: 6
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ 0 1 0 0 6 0 0 1
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 CTL EXCL 12/715 10/2000 ParamProductionCell-PT-4-CTLFireability-2024-01 2022453 m, 160761 m/sec, 7288588 t fired, .
[lola][.]
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[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ 0 1 0 0 6 0 0 1
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 CTL EXCL 17/715 12/2000 ParamProductionCell-PT-4-CTLFireability-2024-01 2409739 m, 77457 m/sec, 10427164 t fired, .
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[lola][I] FINISHED task # 60 (type EQUN) for ParamProductionCell-PT-4-CTLFireability-2023-14
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ 0 1 0 0 6 0 0 1
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 CTL EXCL 22/715 12/2000 ParamProductionCell-PT-4-CTLFireability-2024-01 2409739 m, 0 m/sec, 14014461 t fired, .
[lola][.]
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[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF 0 1 0 0 1 0 0 0
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ 0 1 0 0 6 0 0 1
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 4 CTL EXCL 27/715 12/2000 ParamProductionCell-PT-4-CTLFireability-2024-01 2409739 m, 0 m/sec, 17844447 t fired, .
[lola][.]
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[lola][I] FINISHED task # 4 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-01
[lola][I] result : true
[lola][I] markings : 2409739
[lola][I] fired transitions : 19258830
[lola][I] time used : 29
[lola][I] memory pages used : 12
[lola][I] LAUNCH task # 1 (type EXCL) for 0 ParamProductionCell-PT-4-CTLFireability-2024-00
[lola][I] time limit : 887 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-00
[lola][I] result : true
[lola][I] markings : 408
[lola][I] fired transitions : 415
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 10 (type EXCL) for 9 ParamProductionCell-PT-4-CTLFireability-2024-03
[lola][I] time limit : 1183 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 10 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-03
[lola][I] result : true
[lola][I] markings : 356
[lola][I] fired transitions : 715
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 62 (type EXCL) for 33 ParamProductionCell-PT-4-CTLFireability-2024-11
[lola][I] time limit : 1775 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 62 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2024-11
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 48 (type EXCL) for 47 ParamProductionCell-PT-4-CTLFireability-2023-13
[lola][I] time limit : 3550 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-00: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-01: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ true CONJ
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 3/3550 2/2000 ParamProductionCell-PT-4-CTLFireability-2023-13 293433 m, 58686 m/sec, 1979399 t fired, .
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[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-01: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ true CONJ
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 8/3550 4/2000 ParamProductionCell-PT-4-CTLFireability-2023-13 691281 m, 79569 m/sec, 5674090 t fired, .
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[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-02: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-03: EGEF true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-04: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-05: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-08: CTL true CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-09: INITIAL true preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-10: INITIAL false preprocessing
[lola][.] ParamProductionCell-PT-4-CTLFireability-2024-11: CONJ true CONJ
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-12: CTL false CTL model checker
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-14: EF true findpath
[lola][.] ParamProductionCell-PT-4-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 13/3550 5/2000 ParamProductionCell-PT-4-CTLFireability-2023-13 967774 m, 55298 m/sec, 9893366 t fired, .
[lola][.]
[lola][.] Time elapsed: 63 secs. Pages in use: 12
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[lola][I] FINISHED task # 48 (type EXCL) for ParamProductionCell-PT-4-CTLFireability-2023-13
[lola][I] result : true
[lola][I] markings : 976022
[lola][I] fired transitions : 12830435
[lola][I] time used : 16
[lola][I] memory pages used : 5
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ParamProductionCell-PT-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408000042"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-4.tgz
mv ParamProductionCell-PT-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;