MCC'2024- Execution of r269-smll-171654408000034

About the Execution of LoLA for ParamProductionCell-PT-3

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
718.512	61028.00	110352.00	162.70	TFFFFFFFTFTFTFTT	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r269-smll-171654408000034.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ParamProductionCell-PT-3, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r269-smll-171654408000034
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 508K
-rw-r--r-- 1 mcc users 6.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 59K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Apr 23 07:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 23 07:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Apr 23 07:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 23 07:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.5K Apr 12 20:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 46K Apr 12 20:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Apr 12 20:26 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Apr 12 20:26 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 23 07:41 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 23 07:41 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 2 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 174K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-00
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-01
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-02
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-03
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-04
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-05
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-06
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-07
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-08
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-09
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-10
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2024-11
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2023-12
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2023-13
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2023-14
FORMULA_NAME ParamProductionCell-PT-3-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717054091888

FORMULA ParamProductionCell-PT-3-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2023-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ParamProductionCell-PT-3-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-3-CTLFireability-2024-00: EF true findpath[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-04: CONJ false CTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-3-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-3-CTLFireability-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-11: CONJ false state space / EG[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-3-CTLFireability-2023-12: EF true findpath[0m
[[35mlola[0m] [1m[31mParamProductionCell-PT-3-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-3-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mParamProductionCell-PT-3-CTLFireability-2023-15: CONJ true CONJ[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 61 secs. Pages in use: 7

BK_STOP 1717054152916

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 35 (type CNST) for 34 ParamProductionCell-PT-3-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 35 (type CNST) for ParamProductionCell-PT-3-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 ParamProductionCell-PT-3-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 162 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 81 (type EQUN) for 28 ParamProductionCell-PT-3-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 82 (type FNDP) for 0 ParamProductionCell-PT-3-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 83 (type EQUN) for 0 ParamProductionCell-PT-3-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2557
[[35mlola[0m][I] fired transitions : 7162
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 ParamProductionCell-PT-3-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 170 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 82 (type FNDP) for ParamProductionCell-PT-3-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 83 (type EQUN) for ParamProductionCell-PT-3-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][I] LAUNCH task # 87 (type EQUN) for 12 ParamProductionCell-PT-3-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 89 (type EQUN) for 12 ParamProductionCell-PT-3-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 81 (type EQUN) for ParamProductionCell-PT-3-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 97 (type EQUN) for 37 ParamProductionCell-PT-3-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 89 (type EQUN) for ParamProductionCell-PT-3-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 90 (type FNDP) for 48 ParamProductionCell-PT-3-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 97 (type EQUN) for ParamProductionCell-PT-3-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 94 (type FNDP) for 37 ParamProductionCell-PT-3-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 94 (type FNDP) for ParamProductionCell-PT-3-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 91 (type EQUN) for 48 ParamProductionCell-PT-3-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 91 (type EQUN) for ParamProductionCell-PT-3-CTLFireability-2023-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mParamProductionCell-PT-3-CTLFireability-2024-00: EF true findpath[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mParamProductionCell-PT-3-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[32mParamProductionCell-PT-3-CTLFireability-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-04: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-11: CONJ 0 1 0 0 5 0 0 3
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2023-12: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2023-15: CONJ 0 5 0 0 5 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/210 3/2000 ParamProductionCell-PT-3-CTLFireability-2024-01 639406 m, 127881 m/sec, 2780949 t fired, .
[[35mlola[0m][.] 87 EF STEQ 5/3577 0/5 ParamProductionCell-PT-3-CTLFireability-2024-04 sara not yet started (preprocessing).
[[35mlola[0m][.] 90 EF FNDP 5/3577 0/5 ParamProductionCell-PT-3-CTLFireability-2023-12 2 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 28 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 90 (type FNDP) for ParamProductionCell-PT-3-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 2
[[35mlola[0m][I] time used : 6
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mParamProductionCell-PT-3-CTLFireability-2024-00: EF true findpath[0m
[[35mlola[0m][.] [1m[31mParamProductionCell-PT-3-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mParamProductionCell-PT-3-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[32mParamProductionCell-PT-3-CTLFireability-2024-10: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mParamProductionCell-PT-3-CTLFireability-2023-12: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-04: CONJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2024-11: CONJ 0 1 0 0 5 0 0 3
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/223 7/2000 ParamProductionCell-PT-3-CTLFireability-2024-01 1369955 m, 146109 m/sec, 6550452 t fired, .
[[35mlola[0m][.] 87 EF STEQ 10/3577 0/5 ParamProductionCell-PT-3-CTLFireability-2024-04 sara not yet started (preprocessing).
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[[35mlola[0m][I] result : false
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[[35mlola[0m][I] fired transitions : 7388654
[[35mlola[0m][I] time used : 11
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[[35mlola[0m][I] LAUNCH task # 72 (type EXCL) for 57 ParamProductionCell-PT-3-CTLFireability-2023-15
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[[35mlola[0m][I] FINISHED task # 72 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-2023-15
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] time limit : 254 sec
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[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 57 ParamProductionCell-PT-3-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 324 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 87 (type EQUN) for ParamProductionCell-PT-3-CTLFireability-2024-04
[[35mlola[0m][I] result : unknown
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[[35mlola[0m][.] [1m[32mParamProductionCell-PT-3-CTLFireability-2024-00: EF true findpath[0m
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[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 60 CTL EXCL 4/324 3/2000 ParamProductionCell-PT-3-CTLFireability-2023-15 510770 m, 102154 m/sec, 2415418 t fired, .
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[[35mlola[0m][.] ParamProductionCell-PT-3-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.]
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[[35mlola[0m][.] 60 CTL EXCL 9/324 6/2000 ParamProductionCell-PT-3-CTLFireability-2023-15 1121855 m, 122217 m/sec, 5874250 t fired, .
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[[35mlola[0m][I] fired transitions : 8247032
[[35mlola[0m][I] time used : 12
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[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 ParamProductionCell-PT-3-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 355 sec
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[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 37058
[[35mlola[0m][I] fired transitions : 88170
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 ParamProductionCell-PT-3-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 394 sec
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[[35mlola[0m][.] 52 CTL EXCL 2/394 2/2000 ParamProductionCell-PT-3-CTLFireability-2023-13 250531 m, 50106 m/sec, 979090 t fired, .
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[[35mlola[0m][.] 52 CTL EXCL 7/394 5/2000 ParamProductionCell-PT-3-CTLFireability-2023-13 997922 m, 149478 m/sec, 4579969 t fired, .
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[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1465206
[[35mlola[0m][I] fired transitions : 7387857
[[35mlola[0m][I] time used : 11
[[35mlola[0m][I] memory pages used : 7
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 ParamProductionCell-PT-3-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 442 sec
[[35mlola[0m][I] memory limit: 2000 pages
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[[35mlola[0m][.] 20 CTL EXCL 1/442 1/2000 ParamProductionCell-PT-3-CTLFireability-2024-05 94370 m, 18874 m/sec, 615402 t fired, .
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[[35mlola[0m][I] time used : 4
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[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 12 ParamProductionCell-PT-3-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 505 sec
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[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
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[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ParamProductionCell-PT-3-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 707 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 436
[[35mlola[0m][I] fired transitions : 872
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 93 (type EXCL) for 37 ParamProductionCell-PT-3-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 884 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 93 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 609
[[35mlola[0m][I] fired transitions : 625
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 ParamProductionCell-PT-3-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 1179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 417
[[35mlola[0m][I] fired transitions : 837
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 ParamProductionCell-PT-3-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 1769 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 36463
[[35mlola[0m][I] fired transitions : 70877
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 ParamProductionCell-PT-3-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 3539 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for ParamProductionCell-PT-3-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 191
[[35mlola[0m][I] fired transitions : 192
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ParamProductionCell-PT-3"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ParamProductionCell-PT-3, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r269-smll-171654408000034"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ParamProductionCell-PT-3.tgz
mv ParamProductionCell-PT-3 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;