Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r267-smll-171654405700130.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool greatspnxred
Input is PermAdmissibility-COL-10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r267-smll-171654405700130
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 480K
-rw-r--r-- 1 mcc users 7.0K Apr 12 09:18 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Apr 12 09:18 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Apr 12 09:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Apr 12 09:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Apr 23 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 23 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.6K Apr 12 09:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 98K Apr 12 09:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Apr 12 09:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Apr 12 09:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 23 07:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 23 07:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 37K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-00
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-01
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-02
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-03
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-04
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-05
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-06
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-07
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-08
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-09
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-10
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-11
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-12
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-13
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-14
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1716668403529

Invoking MCC driver with
BK_TOOL=greatspnxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PermAdmissibility-COL-10
BK_MEMORY_CONFINEMENT=16384
Applying reductions before tool greatspn
Invoking reducer
Running Version 202405141337
[2024-05-25 20:20:05] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2024-05-25 20:20:05] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-25 20:20:05] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2024-05-25 20:20:06] [WARNING] Using fallBack plugin, rng conformance not checked
[2024-05-25 20:20:06] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 979 ms
[2024-05-25 20:20:06] [INFO ] Imported 40 HL places and 16 HL transitions for a total of 208 PT places and 1024.0 transition bindings in 31 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 38 ms.
[2024-05-25 20:20:07] [INFO ] Built PT skeleton of HLPN with 40 places and 16 transitions 83 arcs in 6 ms.
[2024-05-25 20:20:07] [INFO ] Skeletonized 16 HLPN properties in 4 ms.
Computed a total of 40 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 40 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 11 formulas.
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 12 properties that can be checked using skeleton over-approximation.
Computed a total of 40 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 40 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Reduction of identical properties reduced properties to check from 19 to 18
RANDOM walk for 40003 steps (224 resets) in 513 ms. (77 steps per ms) remains 2/18 properties
BEST_FIRST walk for 1647 steps (1 resets) in 27 ms. (58 steps per ms) remains 0/2 properties
[2024-05-25 20:20:07] [INFO ] Flatten gal took : 32 ms
[2024-05-25 20:20:07] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2024-05-25 20:20:07] [INFO ] Flatten gal took : 8 ms
Symmetric sort wr.t. initial and guards and successors and join/free detected :input
Symmetric sort wr.t. initial detected :input
Symmetric sort wr.t. initial and guards detected :input
Applying symmetric unfolding of full symmetric sort :input domain size was 8
[2024-05-25 20:20:07] [INFO ] Unfolded HLPN to a Petri net with 40 places and 16 transitions 83 arcs in 22 ms.
[2024-05-25 20:20:07] [INFO ] Unfolded 14 HLPN properties in 1 ms.
Support contains 32 out of 40 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 40/40 places, 16/16 transitions.
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 32 transition count 16
Applied a total of 8 rules in 20 ms. Remains 32 /40 variables (removed 8) and now considering 16/16 (removed 0) transitions.
// Phase 1: matrix 16 rows 32 cols
[2024-05-25 20:20:07] [INFO ] Computed 16 invariants in 11 ms
[2024-05-25 20:20:07] [INFO ] Implicit Places using invariants in 219 ms returned []
[2024-05-25 20:20:07] [INFO ] Invariant cache hit.
[2024-05-25 20:20:07] [INFO ] Implicit Places using invariants and state equation in 95 ms returned []
Implicit Place search using SMT with State Equation took 363 ms to find 0 implicit places.
Running 15 sub problems to find dead transitions.
[2024-05-25 20:20:07] [INFO ] Invariant cache hit.
At refinement iteration 0 (INCLUDED_ONLY) 0/31 variables, 12/12 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/31 variables, 0/12 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 2 (OVERLAPS) 1/32 variables, 4/16 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/32 variables, 0/16 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 4 (OVERLAPS) 16/48 variables, 32/48 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/48 variables, 0/48 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 6 (OVERLAPS) 0/48 variables, 0/48 constraints. Problems are: Problem set: 0 solved, 15 unsolved
No progress, stopping.
After SMT solving in domain Real declared 48/48 variables, and 48 constraints, problems are : Problem set: 0 solved, 15 unsolved in 445 ms.
Refiners :[Generalized P Invariants (flows): 16/16 constraints, State Equation: 32/32 constraints, PredecessorRefiner: 15/15 constraints, Known Traps: 0/0 constraints]
Escalating to Integer solving :Problem set: 0 solved, 15 unsolved
At refinement iteration 0 (INCLUDED_ONLY) 0/31 variables, 12/12 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 1 (INCLUDED_ONLY) 0/31 variables, 0/12 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 2 (OVERLAPS) 1/32 variables, 4/16 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 3 (INCLUDED_ONLY) 0/32 variables, 0/16 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 4 (OVERLAPS) 16/48 variables, 32/48 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 5 (INCLUDED_ONLY) 0/48 variables, 15/63 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 6 (INCLUDED_ONLY) 0/48 variables, 0/63 constraints. Problems are: Problem set: 0 solved, 15 unsolved
At refinement iteration 7 (OVERLAPS) 0/48 variables, 0/63 constraints. Problems are: Problem set: 0 solved, 15 unsolved
No progress, stopping.
After SMT solving in domain Int declared 48/48 variables, and 63 constraints, problems are : Problem set: 0 solved, 15 unsolved in 416 ms.
Refiners :[Generalized P Invariants (flows): 16/16 constraints, State Equation: 32/32 constraints, PredecessorRefiner: 15/15 constraints, Known Traps: 0/0 constraints]
After SMT, in 914ms problems are : Problem set: 0 solved, 15 unsolved
Search for dead transitions found 0 dead transitions in 931ms
Starting structural reductions in LTL mode, iteration 1 : 32/40 places, 16/16 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1334 ms. Remains : 32/40 places, 16/16 transitions.
Support contains 32 out of 32 places after structural reductions.
[2024-05-25 20:20:08] [INFO ] Flatten gal took : 20 ms
[2024-05-25 20:20:08] [INFO ] Flatten gal took : 10 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Reduction of identical properties reduced properties to check from 37 to 32
RANDOM walk for 40000 steps (224 resets) in 338 ms. (117 steps per ms) remains 4/32 properties
BEST_FIRST walk for 4086 steps (2 resets) in 18 ms. (215 steps per ms) remains 0/4 properties
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 5 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 8 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Computed a total of 32 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 32 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 3 formulas.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 2 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 32/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 5 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 5 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 32/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 5 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 31/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 5 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 32/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 24 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.1 ms
Discarding 8 places :
Also discarding 4 output transitions
Drop transitions (Output transitions of discarded places.) removed 4 transitions
Ensure Unique test removed 2 places
Applied a total of 1 rules in 17 ms. Remains 22 /32 variables (removed 10) and now considering 12/16 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 22/32 places, 12/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 3 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 12 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 16 are kept as prefixes of interest. Removing 16 places using SCC suffix rule.1 ms
Discarding 16 places :
Also discarding 8 output transitions
Drop transitions (Output transitions of discarded places.) removed 8 transitions
Ensure Unique test removed 2 places
Applied a total of 1 rules in 3 ms. Remains 14 /32 variables (removed 18) and now considering 8/16 (removed 8) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 14/32 places, 8/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 1 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 2 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 8 transitions.
RANDOM walk for 268 steps (0 resets) in 8 ms. (29 steps per ms) remains 0/1 properties
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Applied a total of 0 rules in 3 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 31/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 3 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 2 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 31/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 5 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 2 places
Applied a total of 0 rules in 2 ms. Remains 30 /32 variables (removed 2) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 30/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 3 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
RANDOM walk for 620 steps (0 resets) in 6 ms. (88 steps per ms) remains 0/1 properties
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 32/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 3 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 1 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 31/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 3 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 24 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.1 ms
Discarding 8 places :
Also discarding 4 output transitions
Drop transitions (Output transitions of discarded places.) removed 4 transitions
Ensure Unique test removed 2 places
Applied a total of 1 rules in 3 ms. Remains 22 /32 variables (removed 10) and now considering 12/16 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 22/32 places, 12/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 3 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 3 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 12 transitions.
RANDOM walk for 400 steps (0 resets) in 4 ms. (80 steps per ms) remains 0/1 properties
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Applied a total of 0 rules in 2 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 31/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 3 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 2 places
Applied a total of 0 rules in 3 ms. Remains 30 /32 variables (removed 2) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 30/32 places, 16/16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 4 ms
[2024-05-25 20:20:09] [INFO ] Input system was already deterministic with 16 transitions.
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 8 ms
[2024-05-25 20:20:09] [INFO ] Flatten gal took : 7 ms
[2024-05-25 20:20:09] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 6 ms.
[2024-05-25 20:20:09] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 32 places, 16 transitions and 75 arcs took 5 ms.
Total runtime 4016 ms.
There are residual formulas that ITS could not solve within timeout
----------------------------------------------------------------------
GreatSPN-meddly tool, MCC 2023
----------------------------------------------------------------------

Running PermAdmissibility-COL-10

IS_COLORED=
IS_NUPN=

LOADING PETRI NET FILE /home/mcc/execution/407/model.pnml (PNML) ...
PNML VERSION 2009, P/T NET.
COLOR CLASSES: 0
CONSTANTS: 0
PLACES: 32
TRANSITIONS: 16
COLOR VARS: 0
MEASURES: 0
LOADING TIME: [User 0.000s, Sys 0.001s]


SAVING FILE /home/mcc/execution/407/model (.net / .def) ...
EXPORT TIME: [User 0.000s, Sys 0.000s]


----------------------------------------------------------------------
GreatSPN/Meddly.
Copyright (C) 1987-2022, University of Torino, Italy.
website: https://github.com/greatspn/SOURCES

Based on MEDDLY version 0.16.0
Copyright (C) 2009, Iowa State University Research Foundation, Inc.
website: http://meddly.sourceforge.net

Process ID: 527
MODEL NAME: /home/mcc/execution/407/model
32 places, 16 transitions.

Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Creating all event NSFs..
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Split: SplitSubtract
Start RS construction.
Building monolithic NSF...
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-01 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-04 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-00 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-02 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-07 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-06 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-11 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-13 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-10 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-03 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
FORMULA PermAdmissibility-COL-10-CTLFireability-2024-14 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING UNFOLDING_TO_PT USE_NUPN TOPOLOGICAL
Ok.
EXITCODE: 0
----------------------------------------------------------------------

BK_STOP 1716668627283

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202405141337.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202405141337
+ echo 'Running Version 202405141337'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="greatspnxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool greatspnxred"
echo " Input is PermAdmissibility-COL-10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r267-smll-171654405700130"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-10.tgz
mv PermAdmissibility-COL-10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;