About the Execution of LoLA for PGCD-PT-D05N025
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16202.592 | 269100.00 | 273518.00 | 804.50 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654354100788.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PGCD-PT-D05N025, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654354100788
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 456K
-rw-r--r-- 1 mcc users 8.2K Apr 11 15:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K Apr 11 15:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Apr 11 15:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Apr 11 15:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K May 6 10:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 6 10:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 6 10:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 6 10:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.9K Apr 11 15:31 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 102K Apr 11 15:31 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Apr 11 15:30 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 77K Apr 11 15:30 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 6 10:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 6 10:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 12K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-00
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-01
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-02
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-03
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-04
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-05
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-06
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-07
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-08
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-09
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-10
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-11
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-12
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-13
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-14
FORMULA_NAME PGCD-PT-D05N025-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717104602807
BK_STOP 1717104871907
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 PGCD-PT-D05N025-LTLFireability-05
[[35mlola[0m][I] time limit : 119 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 6 (type CNST) for 3 PGCD-PT-D05N025-LTLFireability-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 6 (type CNST) for PGCD-PT-D05N025-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for PGCD-PT-D05N025-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 679
[[35mlola[0m][I] fired transitions : 1016
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 61 PGCD-PT-D05N025-LTLFireability-15
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for PGCD-PT-D05N025-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 31900
[[35mlola[0m][I] fired transitions : 78615
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 58 PGCD-PT-D05N025-LTLFireability-14
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for PGCD-PT-D05N025-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 15298
[[35mlola[0m][I] fired transitions : 36846
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 52 PGCD-PT-D05N025-LTLFireability-12
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for PGCD-PT-D05N025-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 37
[[35mlola[0m][I] fired transitions : 37
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 PGCD-PT-D05N025-LTLFireability-11
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for PGCD-PT-D05N025-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 53
[[35mlola[0m][I] fired transitions : 53
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 PGCD-PT-D05N025-LTLFireability-09
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for PGCD-PT-D05N025-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 55
[[35mlola[0m][I] fired transitions : 55
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 36 PGCD-PT-D05N025-LTLFireability-08
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for PGCD-PT-D05N025-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 31
[[35mlola[0m][I] fired transitions : 31
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 PGCD-PT-D05N025-LTLFireability-06
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for PGCD-PT-D05N025-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 64
[[35mlola[0m][I] fired transitions : 64
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 PGCD-PT-D05N025-LTLFireability-04
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for PGCD-PT-D05N025-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 53
[[35mlola[0m][I] fired transitions : 53
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 PGCD-PT-D05N025-LTLFireability-02
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for PGCD-PT-D05N025-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 15607
[[35mlola[0m][I] fired transitions : 38031
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 PGCD-PT-D05N025-LTLFireability-00
[[35mlola[0m][I] time limit : 719 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for PGCD-PT-D05N025-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 PGCD-PT-D05N025-LTLFireability-03
[[35mlola[0m][I] time limit : 899 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for PGCD-PT-D05N025-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 18309
[[35mlola[0m][I] fired transitions : 27894
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 56 (type EXCL) for 55 PGCD-PT-D05N025-LTLFireability-13
[[35mlola[0m][I] time limit : 1199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 4/1199 14/2000 PGCD-PT-D05N025-LTLFireability-13 2125060 m, 425012 m/sec, 6348194 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 9/1199 27/2000 PGCD-PT-D05N025-LTLFireability-13 4012821 m, 377552 m/sec, 12049558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 14/1199 37/2000 PGCD-PT-D05N025-LTLFireability-13 5562741 m, 309984 m/sec, 16739466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 19/1199 47/2000 PGCD-PT-D05N025-LTLFireability-13 7207535 m, 328958 m/sec, 21732242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 24/1199 58/2000 PGCD-PT-D05N025-LTLFireability-13 8855029 m, 329498 m/sec, 26754752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 29/1199 68/2000 PGCD-PT-D05N025-LTLFireability-13 10464705 m, 321935 m/sec, 31705280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 34/1199 81/2000 PGCD-PT-D05N025-LTLFireability-13 12403340 m, 387727 m/sec, 37544696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 39/1199 92/2000 PGCD-PT-D05N025-LTLFireability-13 14121212 m, 343574 m/sec, 42742698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 44/1199 104/2000 PGCD-PT-D05N025-LTLFireability-13 15888365 m, 353430 m/sec, 48085543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 49/1199 114/2000 PGCD-PT-D05N025-LTLFireability-13 17557414 m, 333809 m/sec, 53161465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 54/1199 126/2000 PGCD-PT-D05N025-LTLFireability-13 19401651 m, 368847 m/sec, 58854825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 59/1199 138/2000 PGCD-PT-D05N025-LTLFireability-13 21205522 m, 360774 m/sec, 64412195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 64/1199 149/2000 PGCD-PT-D05N025-LTLFireability-13 22885799 m, 336055 m/sec, 69575227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 69/1199 160/2000 PGCD-PT-D05N025-LTLFireability-13 24620291 m, 346898 m/sec, 74882118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 74/1199 171/2000 PGCD-PT-D05N025-LTLFireability-13 26323858 m, 340713 m/sec, 80091191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 79/1199 183/2000 PGCD-PT-D05N025-LTLFireability-13 28170174 m, 369263 m/sec, 85666332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 84/1199 195/2000 PGCD-PT-D05N025-LTLFireability-13 30035447 m, 373054 m/sec, 91357632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 89/1199 207/2000 PGCD-PT-D05N025-LTLFireability-13 31837961 m, 360502 m/sec, 96849653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 94/1199 218/2000 PGCD-PT-D05N025-LTLFireability-13 33514740 m, 335355 m/sec, 101957956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 99/1199 228/2000 PGCD-PT-D05N025-LTLFireability-13 35122912 m, 321634 m/sec, 106845965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 104/1199 239/2000 PGCD-PT-D05N025-LTLFireability-13 36708727 m, 317163 m/sec, 111684375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 109/1199 248/2000 PGCD-PT-D05N025-LTLFireability-13 38230357 m, 304326 m/sec, 116347733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 114/1199 258/2000 PGCD-PT-D05N025-LTLFireability-13 39711929 m, 296314 m/sec, 120917170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 119/1199 268/2000 PGCD-PT-D05N025-LTLFireability-13 41289448 m, 315503 m/sec, 125748591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 124/1199 278/2000 PGCD-PT-D05N025-LTLFireability-13 42862182 m, 314546 m/sec, 130527182 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 129/1199 290/2000 PGCD-PT-D05N025-LTLFireability-13 44595298 m, 346623 m/sec, 135745646 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 290
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 134/1199 300/2000 PGCD-PT-D05N025-LTLFireability-13 46204745 m, 321889 m/sec, 140628930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 139/1199 312/2000 PGCD-PT-D05N025-LTLFireability-13 48055377 m, 370126 m/sec, 146274089 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 144/1199 323/2000 PGCD-PT-D05N025-LTLFireability-13 49728644 m, 334653 m/sec, 151360031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 323
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 149/1199 333/2000 PGCD-PT-D05N025-LTLFireability-13 51332616 m, 320794 m/sec, 156236785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 333
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 154/1199 344/2000 PGCD-PT-D05N025-LTLFireability-13 52892854 m, 312047 m/sec, 160991161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 344
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 159/1199 353/2000 PGCD-PT-D05N025-LTLFireability-13 54416171 m, 304663 m/sec, 165634912 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 353
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 164/1199 363/2000 PGCD-PT-D05N025-LTLFireability-13 55915715 m, 299908 m/sec, 170204306 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 363
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 169/1199 373/2000 PGCD-PT-D05N025-LTLFireability-13 57396367 m, 296130 m/sec, 174737248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 373
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 174/1199 382/2000 PGCD-PT-D05N025-LTLFireability-13 58881908 m, 297108 m/sec, 179313692 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 179/1199 395/2000 PGCD-PT-D05N025-LTLFireability-13 60812821 m, 386182 m/sec, 185133501 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 395
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 184/1199 407/2000 PGCD-PT-D05N025-LTLFireability-13 62670171 m, 371470 m/sec, 190754043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 407
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 189/1199 419/2000 PGCD-PT-D05N025-LTLFireability-13 64463695 m, 358704 m/sec, 196185706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 419
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 194/1199 430/2000 PGCD-PT-D05N025-LTLFireability-13 66304651 m, 368191 m/sec, 201732238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 430
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 199/1199 441/2000 PGCD-PT-D05N025-LTLFireability-13 67965449 m, 332159 m/sec, 206768947 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 441
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 204/1199 453/2000 PGCD-PT-D05N025-LTLFireability-13 69733195 m, 353549 m/sec, 212103733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 209/1199 464/2000 PGCD-PT-D05N025-LTLFireability-13 71400030 m, 333367 m/sec, 217144696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 464
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 214/1199 475/2000 PGCD-PT-D05N025-LTLFireability-13 73143623 m, 348718 m/sec, 222401604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 475
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 219/1199 487/2000 PGCD-PT-D05N025-LTLFireability-13 75068091 m, 384893 m/sec, 228202754 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 487
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 224/1199 500/2000 PGCD-PT-D05N025-LTLFireability-13 77045249 m, 395431 m/sec, 234178372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 500
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 229/1199 512/2000 PGCD-PT-D05N025-LTLFireability-13 78922105 m, 375371 m/sec, 239930110 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 512
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 234/1199 525/2000 PGCD-PT-D05N025-LTLFireability-13 80877033 m, 390985 m/sec, 245941862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 525
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 239/1199 538/2000 PGCD-PT-D05N025-LTLFireability-13 82914939 m, 407581 m/sec, 252182709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 538
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 244/1199 552/2000 PGCD-PT-D05N025-LTLFireability-13 85007507 m, 418513 m/sec, 258482994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 552
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 249/1199 563/2000 PGCD-PT-D05N025-LTLFireability-13 86733648 m, 345228 m/sec, 263732392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 563
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 254/1199 576/2000 PGCD-PT-D05N025-LTLFireability-13 88819624 m, 417195 m/sec, 270157572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 576
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 259/1199 589/2000 PGCD-PT-D05N025-LTLFireability-13 90713095 m, 378694 m/sec, 275985889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 589
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-LTLFireability-00: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-08: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 56 LTL EXCL 264/1199 601/2000 PGCD-PT-D05N025-LTLFireability-13 92529127 m, 363206 m/sec, 281538077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 601
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-PT-D05N025"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PGCD-PT-D05N025, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654354100788"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PGCD-PT-D05N025.tgz
mv PGCD-PT-D05N025 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;