About the Execution of LoLA for PGCD-PT-D05N025
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.216 | 344533.00 | 347936.00 | 1134.70 | T???????????T?T? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654354100786.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PGCD-PT-D05N025, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654354100786
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 456K
-rw-r--r-- 1 mcc users 8.2K Apr 11 15:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K Apr 11 15:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Apr 11 15:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Apr 11 15:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K May 6 10:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 6 10:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 6 10:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 6 10:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.9K Apr 11 15:31 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 102K Apr 11 15:31 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Apr 11 15:30 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 77K Apr 11 15:30 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 6 10:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 6 10:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 12K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-00
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-01
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-02
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-03
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-04
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-05
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-06
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-07
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-08
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-09
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-10
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-11
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-12
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-13
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-14
FORMULA_NAME PGCD-PT-D05N025-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717104484800
FORMULA PGCD-PT-D05N025-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D05N025-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D05N025-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717104829333
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 36 PGCD-PT-D05N025-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 150 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 52 (type FNDP) for 36 PGCD-PT-D05N025-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 53 (type EQUN) for 36 PGCD-PT-D05N025-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for PGCD-PT-D05N025-CTLFireability-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 52 (type FNDP) for PGCD-PT-D05N025-CTLFireability-2024-12 (obsolete)
[[35mlola[0m][W] CANCELED task # 53 (type EQUN) for PGCD-PT-D05N025-CTLFireability-2024-12 (obsolete)
[[35mlola[0m][I] FINISHED task # 52 (type FNDP) for PGCD-PT-D05N025-CTLFireability-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 PGCD-PT-D05N025-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for PGCD-PT-D05N025-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 PGCD-PT-D05N025-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 53 (type EQUN) for PGCD-PT-D05N025-CTLFireability-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 59 (type EQUN) for 39 PGCD-PT-D05N025-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 39 PGCD-PT-D05N025-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type EQUN) for PGCD-PT-D05N025-CTLFireability-2024-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 0 PGCD-PT-D05N025-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for PGCD-PT-D05N025-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 59 (type EQUN) for PGCD-PT-D05N025-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 4/257 7/2000 PGCD-PT-D05N025-CTLFireability-2024-02 1354606 m, 270921 m/sec, 10181216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 9/257 13/2000 PGCD-PT-D05N025-CTLFireability-2024-02 2834810 m, 296040 m/sec, 19192122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 14/257 19/2000 PGCD-PT-D05N025-CTLFireability-2024-02 4247794 m, 282596 m/sec, 28730725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 19/257 24/2000 PGCD-PT-D05N025-CTLFireability-2024-02 5609454 m, 272332 m/sec, 37104819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 24/257 30/2000 PGCD-PT-D05N025-CTLFireability-2024-02 6933640 m, 264837 m/sec, 45193765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 29/257 36/2000 PGCD-PT-D05N025-CTLFireability-2024-02 8293966 m, 272065 m/sec, 53967198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 34/257 41/2000 PGCD-PT-D05N025-CTLFireability-2024-02 9613174 m, 263841 m/sec, 61980807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 39/257 47/2000 PGCD-PT-D05N025-CTLFireability-2024-02 10895303 m, 256425 m/sec, 69840875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 44/257 52/2000 PGCD-PT-D05N025-CTLFireability-2024-02 12232469 m, 267433 m/sec, 78665483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 49/257 58/2000 PGCD-PT-D05N025-CTLFireability-2024-02 13523076 m, 258121 m/sec, 86934153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 54/257 63/2000 PGCD-PT-D05N025-CTLFireability-2024-02 14771487 m, 249682 m/sec, 95248091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 59/257 68/2000 PGCD-PT-D05N025-CTLFireability-2024-02 16061832 m, 258069 m/sec, 103279586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 64/257 73/2000 PGCD-PT-D05N025-CTLFireability-2024-02 17281084 m, 243850 m/sec, 111388181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 69/257 78/2000 PGCD-PT-D05N025-CTLFireability-2024-02 18470844 m, 237952 m/sec, 119329922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 74/257 84/2000 PGCD-PT-D05N025-CTLFireability-2024-02 19750360 m, 255903 m/sec, 127479803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 79/257 89/2000 PGCD-PT-D05N025-CTLFireability-2024-02 21009452 m, 251818 m/sec, 135232172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 84/257 94/2000 PGCD-PT-D05N025-CTLFireability-2024-02 22102652 m, 218640 m/sec, 142884601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 89/257 99/2000 PGCD-PT-D05N025-CTLFireability-2024-02 23321066 m, 243682 m/sec, 150913316 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 94/257 103/2000 PGCD-PT-D05N025-CTLFireability-2024-02 24428929 m, 221572 m/sec, 158425165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 99/257 108/2000 PGCD-PT-D05N025-CTLFireability-2024-02 25531741 m, 220562 m/sec, 165743902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 104/257 113/2000 PGCD-PT-D05N025-CTLFireability-2024-02 26659036 m, 225459 m/sec, 173117733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 109/257 117/2000 PGCD-PT-D05N025-CTLFireability-2024-02 27717749 m, 211742 m/sec, 180264310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 114/257 122/2000 PGCD-PT-D05N025-CTLFireability-2024-02 28776347 m, 211719 m/sec, 187381749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 119/257 127/2000 PGCD-PT-D05N025-CTLFireability-2024-02 29937094 m, 232149 m/sec, 194981250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 124/257 131/2000 PGCD-PT-D05N025-CTLFireability-2024-02 31019356 m, 216452 m/sec, 202367783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 129/257 136/2000 PGCD-PT-D05N025-CTLFireability-2024-02 32272102 m, 250549 m/sec, 210564159 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 134/257 141/2000 PGCD-PT-D05N025-CTLFireability-2024-02 33260920 m, 197763 m/sec, 217293071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 139/257 145/2000 PGCD-PT-D05N025-CTLFireability-2024-02 34356353 m, 219086 m/sec, 224453456 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 144/257 150/2000 PGCD-PT-D05N025-CTLFireability-2024-02 35555142 m, 239757 m/sec, 231971155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 149/257 155/2000 PGCD-PT-D05N025-CTLFireability-2024-02 36780401 m, 245051 m/sec, 239878463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 154/257 160/2000 PGCD-PT-D05N025-CTLFireability-2024-02 37786578 m, 201235 m/sec, 246710499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 159/257 164/2000 PGCD-PT-D05N025-CTLFireability-2024-02 38796076 m, 201899 m/sec, 253412533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 164/257 168/2000 PGCD-PT-D05N025-CTLFireability-2024-02 39776151 m, 196015 m/sec, 260303296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 169/257 173/2000 PGCD-PT-D05N025-CTLFireability-2024-02 40901435 m, 225056 m/sec, 267351781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 174/257 177/2000 PGCD-PT-D05N025-CTLFireability-2024-02 41937495 m, 207212 m/sec, 274422697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 179/257 182/2000 PGCD-PT-D05N025-CTLFireability-2024-02 43076690 m, 227839 m/sec, 281714060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 184/257 186/2000 PGCD-PT-D05N025-CTLFireability-2024-02 44038215 m, 192305 m/sec, 288432294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 189/257 191/2000 PGCD-PT-D05N025-CTLFireability-2024-02 45174365 m, 227230 m/sec, 295695792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 194/257 195/2000 PGCD-PT-D05N025-CTLFireability-2024-02 46172824 m, 199691 m/sec, 302491282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 199/257 200/2000 PGCD-PT-D05N025-CTLFireability-2024-02 47358333 m, 237101 m/sec, 310087794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 204/257 204/2000 PGCD-PT-D05N025-CTLFireability-2024-02 48413149 m, 210963 m/sec, 317544111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 210/257 209/2000 PGCD-PT-D05N025-CTLFireability-2024-02 49537532 m, 224876 m/sec, 324988403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 215/257 213/2000 PGCD-PT-D05N025-CTLFireability-2024-02 50504233 m, 193340 m/sec, 331626624 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 220/257 217/2000 PGCD-PT-D05N025-CTLFireability-2024-02 51561998 m, 211553 m/sec, 338540950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 225/257 222/2000 PGCD-PT-D05N025-CTLFireability-2024-02 52651978 m, 217996 m/sec, 345519302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 230/257 226/2000 PGCD-PT-D05N025-CTLFireability-2024-02 53590920 m, 187788 m/sec, 351830690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 235/257 230/2000 PGCD-PT-D05N025-CTLFireability-2024-02 54517499 m, 185315 m/sec, 358131590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 240/257 234/2000 PGCD-PT-D05N025-CTLFireability-2024-02 55476913 m, 191882 m/sec, 364455063 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 245/257 238/2000 PGCD-PT-D05N025-CTLFireability-2024-02 56592712 m, 223159 m/sec, 371909833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 250/257 243/2000 PGCD-PT-D05N025-CTLFireability-2024-02 57584842 m, 198426 m/sec, 378611590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 255/257 247/2000 PGCD-PT-D05N025-CTLFireability-2024-02 58661701 m, 215371 m/sec, 385810461 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for PGCD-PT-D05N025-CTLFireability-2024-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-13: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 39 PGCD-PT-D05N025-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 PGCD-PT-D05N025-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 3339 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for PGCD-PT-D05N025-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 54
[[35mlola[0m][I] fired transitions : 54
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 7 (type EXCL) for PGCD-PT-D05N025-CTLFireability-2024-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 PGCD-PT-D05N025-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 303 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for PGCD-PT-D05N025-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 PGCD-PT-D05N025-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 333 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 5/333 13/2000 PGCD-PT-D05N025-CTLFireability-2024-10 2811637 m, 562327 m/sec, 9761236 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 264
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 10/333 24/2000 PGCD-PT-D05N025-CTLFireability-2024-10 5454516 m, 528575 m/sec, 18201400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 15/333 34/2000 PGCD-PT-D05N025-CTLFireability-2024-10 7943840 m, 497864 m/sec, 26339154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 20/333 44/2000 PGCD-PT-D05N025-CTLFireability-2024-10 10348640 m, 480960 m/sec, 34268401 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 25/333 54/2000 PGCD-PT-D05N025-CTLFireability-2024-10 12712974 m, 472866 m/sec, 42076902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 30/333 64/2000 PGCD-PT-D05N025-CTLFireability-2024-10 15006276 m, 458660 m/sec, 49673788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 35/333 72/2000 PGCD-PT-D05N025-CTLFireability-2024-10 16993608 m, 397466 m/sec, 56468865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 323
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 40/333 80/2000 PGCD-PT-D05N025-CTLFireability-2024-10 18952672 m, 391812 m/sec, 63048277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 45/333 88/2000 PGCD-PT-D05N025-CTLFireability-2024-10 20809855 m, 371436 m/sec, 69576884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 339
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 50/333 96/2000 PGCD-PT-D05N025-CTLFireability-2024-10 22586381 m, 355305 m/sec, 75921060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 55/333 103/2000 PGCD-PT-D05N025-CTLFireability-2024-10 24346366 m, 351997 m/sec, 82220073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 354
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 60/333 110/2000 PGCD-PT-D05N025-CTLFireability-2024-10 25994243 m, 329575 m/sec, 88286135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 361
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 65/333 117/2000 PGCD-PT-D05N025-CTLFireability-2024-10 27658482 m, 332847 m/sec, 94374626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 368
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 70/333 124/2000 PGCD-PT-D05N025-CTLFireability-2024-10 29312195 m, 330742 m/sec, 100391818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 375
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-00: AR true state equation[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D05N025-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-12: EF true state space[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-13: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D05N025-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D05N025-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 75/333 130/2000 PGCD-PT-D05N025-CTLFireability-2024-10 30691269 m, 275814 m/sec, 105530467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 381
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-PT-D05N025"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PGCD-PT-D05N025, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654354100786"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PGCD-PT-D05N025.tgz
mv PGCD-PT-D05N025 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;