About the Execution of LoLA for PGCD-PT-D04N050
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
7042.231 | 74370.00 | 75398.00 | 288.70 | FTFTFFFTFFTFTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654354100780.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PGCD-PT-D04N050, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654354100780
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 528K
-rw-r--r-- 1 mcc users 9.2K Apr 11 15:35 CTLCardinality.txt
-rw-r--r-- 1 mcc users 103K Apr 11 15:35 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Apr 11 15:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K Apr 11 15:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 6 10:02 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 6 10:02 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 6 10:02 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 6 10:02 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 11 15:37 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 120K Apr 11 15:37 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 11 15:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 113K Apr 11 15:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 6 10:02 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 6 10:02 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 9.3K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-00
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-01
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-02
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-03
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-04
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-05
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-06
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-07
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-08
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-09
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-10
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-11
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-12
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-13
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-14
FORMULA_NAME PGCD-PT-D04N050-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717104399908
FORMULA PGCD-PT-D04N050-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-LTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mPGCD-PT-D04N050-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mPGCD-PT-D04N050-LTLFireability-03: CONJ true CONJ[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mPGCD-PT-D04N050-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mPGCD-PT-D04N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 75 secs. Pages in use: 150
BK_STOP 1717104474278
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 PGCD-PT-D04N050-LTLFireability-13
[[35mlola[0m][I] time limit : 149 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 66 (type FNDP) for 61 PGCD-PT-D04N050-LTLFireability-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 61 PGCD-PT-D04N050-LTLFireability-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 17 PGCD-PT-D04N050-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for PGCD-PT-D04N050-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 54 PGCD-PT-D04N050-LTLFireability-14
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 66 (type FNDP) for PGCD-PT-D04N050-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 67 (type EQUN) for PGCD-PT-D04N050-LTLFireability-15 (obsolete)
[[35mlola[0m][I] LAUNCH task # 74 (type FNDP) for 54 PGCD-PT-D04N050-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 75 (type EQUN) for 54 PGCD-PT-D04N050-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type FNDP) for PGCD-PT-D04N050-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 57 (type EXCL) for PGCD-PT-D04N050-LTLFireability-14 (obsolete)
[[35mlola[0m][W] CANCELED task # 75 (type EQUN) for PGCD-PT-D04N050-LTLFireability-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 48 PGCD-PT-D04N050-LTLFireability-12
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 49 (type EXCL) for PGCD-PT-D04N050-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 PGCD-PT-D04N050-LTLFireability-11
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 67 (type EQUN) for PGCD-PT-D04N050-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for PGCD-PT-D04N050-LTLFireability-03
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 75 (type EQUN) for PGCD-PT-D04N050-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 5/239 21/2000 PGCD-PT-D04N050-LTLFireability-11 2999943 m, 599988 m/sec, 9058715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 10/239 40/2000 PGCD-PT-D04N050-LTLFireability-11 5808137 m, 561638 m/sec, 17444575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 15/239 58/2000 PGCD-PT-D04N050-LTLFireability-11 8548061 m, 547984 m/sec, 25622279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 20/239 76/2000 PGCD-PT-D04N050-LTLFireability-11 11187735 m, 527934 m/sec, 33545780 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 25/239 92/2000 PGCD-PT-D04N050-LTLFireability-11 13640530 m, 490559 m/sec, 40987312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 30/239 107/2000 PGCD-PT-D04N050-LTLFireability-11 15834657 m, 438825 m/sec, 47712192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 35/239 125/2000 PGCD-PT-D04N050-LTLFireability-11 18663837 m, 565836 m/sec, 55943365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 40/239 143/2000 PGCD-PT-D04N050-LTLFireability-11 21343584 m, 535949 m/sec, 63626040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for PGCD-PT-D04N050-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 22426080
[[35mlola[0m][I] fired transitions : 66846161
[[35mlola[0m][I] time used : 42
[[35mlola[0m][I] memory pages used : 150
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 PGCD-PT-D04N050-LTLFireability-09
[[35mlola[0m][I] time limit : 254 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for PGCD-PT-D04N050-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 PGCD-PT-D04N050-LTLFireability-08
[[35mlola[0m][I] time limit : 273 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for PGCD-PT-D04N050-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 PGCD-PT-D04N050-LTLFireability-06
[[35mlola[0m][I] time limit : 296 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for PGCD-PT-D04N050-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3831
[[35mlola[0m][I] fired transitions : 6305
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 PGCD-PT-D04N050-LTLFireability-05
[[35mlola[0m][I] time limit : 323 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for PGCD-PT-D04N050-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2518
[[35mlola[0m][I] fired transitions : 4946
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 PGCD-PT-D04N050-LTLFireability-04
[[35mlola[0m][I] time limit : 355 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 3/355 13/2000 PGCD-PT-D04N050-LTLFireability-04 1849925 m, 369985 m/sec, 5538256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 8/355 32/2000 PGCD-PT-D04N050-LTLFireability-04 4606767 m, 551368 m/sec, 13844190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 13/355 49/2000 PGCD-PT-D04N050-LTLFireability-04 7297519 m, 538150 m/sec, 21850570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 18/355 66/2000 PGCD-PT-D04N050-LTLFireability-04 9885902 m, 517676 m/sec, 29615394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 23/355 83/2000 PGCD-PT-D04N050-LTLFireability-04 12422644 m, 507348 m/sec, 37254416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mPGCD-PT-D04N050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mPGCD-PT-D04N050-LTLFireability-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-02: CONJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-03: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-PT-D04N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 28/355 98/2000 PGCD-PT-D04N050-LTLFireability-04 14677395 m, 450950 m/sec, 44151862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for PGCD-PT-D04N050-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16342592
[[35mlola[0m][I] fired transitions : 49258751
[[35mlola[0m][I] time used : 31
[[35mlola[0m][I] memory pages used : 109
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 17 PGCD-PT-D04N050-LTLFireability-03
[[35mlola[0m][I] time limit : 391 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for PGCD-PT-D04N050-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 15 (type EXCL) for 6 PGCD-PT-D04N050-LTLFireability-02
[[35mlola[0m][I] time limit : 440 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 15 (type EXCL) for PGCD-PT-D04N050-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 PGCD-PT-D04N050-LTLFireability-01
[[35mlola[0m][I] time limit : 705 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for PGCD-PT-D04N050-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 PGCD-PT-D04N050-LTLFireability-00
[[35mlola[0m][I] time limit : 881 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for PGCD-PT-D04N050-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 69 (type EXCL) for 17 PGCD-PT-D04N050-LTLFireability-03
[[35mlola[0m][I] time limit : 1175 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 69 (type EXCL) for PGCD-PT-D04N050-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 PGCD-PT-D04N050-LTLFireability-10
[[35mlola[0m][I] time limit : 1762 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for PGCD-PT-D04N050-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 PGCD-PT-D04N050-LTLFireability-07
[[35mlola[0m][I] time limit : 3525 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for PGCD-PT-D04N050-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-PT-D04N050"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PGCD-PT-D04N050, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654354100780"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PGCD-PT-D04N050.tgz
mv PGCD-PT-D04N050 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;