About the Execution of LoLA for PGCD-COL-D03N050
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
0.000 | 247052.00 | 0.00 | 0.00 | [undef] | Cannot compute |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654353900708.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is PGCD-COL-D03N050, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654353900708
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 436K
-rw-r--r-- 1 mcc users 6.1K Apr 11 15:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K Apr 11 15:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Apr 11 15:12 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Apr 11 15:12 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K May 6 10:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K May 6 10:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 6 10:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 6 10:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 11 15:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 168K Apr 11 15:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.1K Apr 11 15:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 27K Apr 11 15:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 6 10:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 6 10:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 8 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 11K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-00
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-01
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-02
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-03
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-04
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-05
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-06
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-07
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-08
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-09
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-10
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-11
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-12
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-13
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-14
FORMULA_NAME PGCD-COL-D03N050-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717102243754
BK_STOP 1717102490806
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/CNST) for 39 PGCD-COL-D03N050-LTLFireability-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 56 (type SKEL/CNST) for PGCD-COL-D03N050-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 57 (type SKEL/CNST) for 46 PGCD-COL-D03N050-LTLFireability-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 57 (type SKEL/CNST) for PGCD-COL-D03N050-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][W] findlow criterion violated for transition 2
[[35mlola[0m][I] Places: 12, Transitions: 12
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][W] findlow criterion violated for 2 clusters
[[35mlola[0m][I] Time for checking findlow: 0
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/SRCH) for 24 PGCD-COL-D03N050-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type SKEL/SRCH) for PGCD-COL-D03N050-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 42 (type CNST) for 39 PGCD-COL-D03N050-LTLFireability-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 49 (type CNST) for 46 PGCD-COL-D03N050-LTLFireability-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 PGCD-COL-D03N050-LTLFireability-00
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type CNST) for PGCD-COL-D03N050-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 49 (type CNST) for PGCD-COL-D03N050-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for PGCD-COL-D03N050-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 104
[[35mlola[0m][I] fired transitions : 105
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 PGCD-COL-D03N050-LTLFireability-15
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 5/239 16/2000 PGCD-COL-D03N050-LTLFireability-15 2387082 m, 477416 m/sec, 5876163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 10/239 30/2000 PGCD-COL-D03N050-LTLFireability-15 4496367 m, 421857 m/sec, 11200013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 15/239 42/2000 PGCD-COL-D03N050-LTLFireability-15 6471933 m, 395113 m/sec, 16259522 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 20/239 55/2000 PGCD-COL-D03N050-LTLFireability-15 8414725 m, 388558 m/sec, 21192843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 25/239 67/2000 PGCD-COL-D03N050-LTLFireability-15 10271184 m, 371291 m/sec, 25981712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 30/239 79/2000 PGCD-COL-D03N050-LTLFireability-15 12072065 m, 360176 m/sec, 30649777 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 35/239 91/2000 PGCD-COL-D03N050-LTLFireability-15 13900788 m, 365744 m/sec, 35337993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 40/239 102/2000 PGCD-COL-D03N050-LTLFireability-15 15688123 m, 357467 m/sec, 39985240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 45/239 114/2000 PGCD-COL-D03N050-LTLFireability-15 17481471 m, 358669 m/sec, 44585326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 50/239 125/2000 PGCD-COL-D03N050-LTLFireability-15 19213826 m, 346471 m/sec, 49104504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 55/239 136/2000 PGCD-COL-D03N050-LTLFireability-15 20930869 m, 343408 m/sec, 53572938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 60/239 147/2000 PGCD-COL-D03N050-LTLFireability-15 22663017 m, 346429 m/sec, 58035174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 65/239 159/2000 PGCD-COL-D03N050-LTLFireability-15 24443114 m, 356019 m/sec, 62584016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 70/239 170/2000 PGCD-COL-D03N050-LTLFireability-15 26102449 m, 331867 m/sec, 67008269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 75/239 181/2000 PGCD-COL-D03N050-LTLFireability-15 27763469 m, 332204 m/sec, 71340856 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 80/239 191/2000 PGCD-COL-D03N050-LTLFireability-15 29397941 m, 326894 m/sec, 75664003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 85/239 202/2000 PGCD-COL-D03N050-LTLFireability-15 31020262 m, 324464 m/sec, 79971330 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 90/239 212/2000 PGCD-COL-D03N050-LTLFireability-15 32671217 m, 330191 m/sec, 84230282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 95/239 223/2000 PGCD-COL-D03N050-LTLFireability-15 34295503 m, 324857 m/sec, 88504283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 100/239 234/2000 PGCD-COL-D03N050-LTLFireability-15 35957406 m, 332380 m/sec, 92809264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 105/239 244/2000 PGCD-COL-D03N050-LTLFireability-15 37589247 m, 326368 m/sec, 97076403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 110/239 255/2000 PGCD-COL-D03N050-LTLFireability-15 39228907 m, 327932 m/sec, 101372805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 115/239 265/2000 PGCD-COL-D03N050-LTLFireability-15 40821414 m, 318501 m/sec, 105568675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 120/239 275/2000 PGCD-COL-D03N050-LTLFireability-15 42389058 m, 313528 m/sec, 109734195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 125/239 286/2000 PGCD-COL-D03N050-LTLFireability-15 44002059 m, 322600 m/sec, 113932773 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 286
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 130/239 296/2000 PGCD-COL-D03N050-LTLFireability-15 45638123 m, 327212 m/sec, 118122090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 135/239 307/2000 PGCD-COL-D03N050-LTLFireability-15 47228015 m, 317978 m/sec, 122290317 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 140/239 317/2000 PGCD-COL-D03N050-LTLFireability-15 48782377 m, 310872 m/sec, 126383859 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 317
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 145/239 327/2000 PGCD-COL-D03N050-LTLFireability-15 50350915 m, 313707 m/sec, 130510503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 150/239 337/2000 PGCD-COL-D03N050-LTLFireability-15 51891203 m, 308057 m/sec, 134612042 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 337
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 155/239 347/2000 PGCD-COL-D03N050-LTLFireability-15 53483820 m, 318523 m/sec, 138721134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 160/239 358/2000 PGCD-COL-D03N050-LTLFireability-15 55113527 m, 325941 m/sec, 142852854 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 358
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 165/239 368/2000 PGCD-COL-D03N050-LTLFireability-15 56634766 m, 304247 m/sec, 146921186 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 368
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 170/239 378/2000 PGCD-COL-D03N050-LTLFireability-15 58135903 m, 300227 m/sec, 150984455 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 175/239 387/2000 PGCD-COL-D03N050-LTLFireability-15 59626196 m, 298058 m/sec, 154994212 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 180/239 397/2000 PGCD-COL-D03N050-LTLFireability-15 61167714 m, 308303 m/sec, 159032198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 397
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 185/239 407/2000 PGCD-COL-D03N050-LTLFireability-15 62743117 m, 315080 m/sec, 163105834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 407
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 190/239 417/2000 PGCD-COL-D03N050-LTLFireability-15 64288374 m, 309051 m/sec, 167116171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 417
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 195/239 427/2000 PGCD-COL-D03N050-LTLFireability-15 65752027 m, 292730 m/sec, 171060209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 427
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 200/239 437/2000 PGCD-COL-D03N050-LTLFireability-15 67303714 m, 310337 m/sec, 175114610 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 437
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 205/239 447/2000 PGCD-COL-D03N050-LTLFireability-15 68815334 m, 302324 m/sec, 179129967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 447
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 210/239 457/2000 PGCD-COL-D03N050-LTLFireability-15 70363005 m, 309534 m/sec, 183179602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 457
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 215/239 467/2000 PGCD-COL-D03N050-LTLFireability-15 71909933 m, 309385 m/sec, 187198748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 467
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 220/239 477/2000 PGCD-COL-D03N050-LTLFireability-15 73501021 m, 318217 m/sec, 191314634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 477
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 225/239 487/2000 PGCD-COL-D03N050-LTLFireability-15 75002057 m, 300207 m/sec, 195255674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 487
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 230/239 496/2000 PGCD-COL-D03N050-LTLFireability-15 76480681 m, 295724 m/sec, 199190422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 496
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 235/239 506/2000 PGCD-COL-D03N050-LTLFireability-15 78008064 m, 305476 m/sec, 203208771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 506
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 54 (type EXCL) for PGCD-COL-D03N050-LTLFireability-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 516
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 46 PGCD-COL-D03N050-LTLFireability-14
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 PGCD-COL-D03N050-LTLFireability-15
[[35mlola[0m][I] time limit : 3359 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for PGCD-COL-D03N050-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 205
[[35mlola[0m][I] fired transitions : 206
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 54 (type EXCL) for PGCD-COL-D03N050-LTLFireability-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mPGCD-COL-D03N050-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-13: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] PGCD-COL-D03N050-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 516
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 39 PGCD-COL-D03N050-LTLFireability-13
[[35mlola[0m][I] time limit : 258 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for PGCD-COL-D03N050-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 41
[[35mlola[0m][I] fired transitions : 64
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 PGCD-COL-D03N050-LTLFireability-11
[[35mlola[0m][I] time limit : 279 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for PGCD-COL-D03N050-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 103
[[35mlola[0m][I] fired transitions : 103
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 PGCD-COL-D03N050-LTLFireability-10
[[35mlola[0m][I] time limit : 304 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for PGCD-COL-D03N050-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 103
[[35mlola[0m][I] fired transitions : 103
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 PGCD-COL-D03N050-LTLFireability-08
[[35mlola[0m][I] time limit : 335 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for PGCD-COL-D03N050-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 103
[[35mlola[0m][I] fired transitions : 103
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 PGCD-COL-D03N050-LTLFireability-06
[[35mlola[0m][I] time limit : 372 sec
[[35mlola[0m][I] memory limit: 2000 pages
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 396 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-COL-D03N050"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is PGCD-COL-D03N050, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654353900708"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PGCD-COL-D03N050.tgz
mv PGCD-COL-D03N050 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;