About the Execution of LoLA for NoC3x3-PT-7B
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
0.000 | 1453213.00 | 0.00 | 0.00 | F????F????FFF??? | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654353800660.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is NoC3x3-PT-7B, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654353800660
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.4M
-rw-r--r-- 1 mcc users 7.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K May 19 07:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 19 16:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 19 07:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 19 18:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 06:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 106K Apr 12 06:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Apr 12 06:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 79K Apr 12 06:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 23 07:41 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:41 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 2.0M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-00
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-01
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-02
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-03
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-04
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-05
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-06
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-07
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-08
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-09
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-10
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-11
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-12
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-13
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-14
FORMULA_NAME NoC3x3-PT-7B-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717098519878
FORMULA NoC3x3-PT-7B-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-7B-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-7B-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-7B-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-7B-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717099973091
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 55 (type CNST) for 52 NoC3x3-PT-7B-LTLFireability-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 55 (type CNST) for NoC3x3-PT-7B-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-05: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-09: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-10: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-11: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[*** LOG ERROR #0001 ***] [2024-05-30 19:50:35] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 NoC3x3-PT-7B-LTLFireability-00
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for NoC3x3-PT-7B-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 15 NoC3x3-PT-7B-LTLFireability-05
[[35mlola[0m][I] time limit : 145 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 73 (type FNDP) for 15 NoC3x3-PT-7B-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 15 NoC3x3-PT-7B-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 80 (type EQUN) for 46 NoC3x3-PT-7B-LTLFireability-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for NoC3x3-PT-7B-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 73 (type FNDP) for NoC3x3-PT-7B-LTLFireability-05 (obsolete)
[[35mlola[0m][W] CANCELED task # 74 (type EQUN) for NoC3x3-PT-7B-LTLFireability-05 (obsolete)
[[35mlola[0m][I] LAUNCH task # 77 (type EXCL) for 46 NoC3x3-PT-7B-LTLFireability-10
[[35mlola[0m][I] time limit : 151 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 85 (type EQUN) for 49 NoC3x3-PT-7B-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type EXCL) for NoC3x3-PT-7B-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 80 (type EQUN) for NoC3x3-PT-7B-LTLFireability-10 (obsolete)
[[35mlola[0m][I] LAUNCH task # 82 (type EXCL) for 49 NoC3x3-PT-7B-LTLFireability-11
[[35mlola[0m][I] time limit : 165 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 73 (type FNDP) for NoC3x3-PT-7B-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 80 (type EQUN) for NoC3x3-PT-7B-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 82 (type EXCL) for NoC3x3-PT-7B-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 85 (type EQUN) for NoC3x3-PT-7B-LTLFireability-11 (obsolete)
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 35 NoC3x3-PT-7B-LTLFireability-09
[[35mlola[0m][I] time limit : 183 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for NoC3x3-PT-7B-LTLFireability-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for NoC3x3-PT-7B-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL) for 63 NoC3x3-PT-7B-LTLFireability-13
[[35mlola[0m][I] time limit : 232 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 85 (type EQUN) for NoC3x3-PT-7B-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 64 (type EXCL) for NoC3x3-PT-7B-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 66 NoC3x3-PT-7B-LTLFireability-14
[[35mlola[0m][I] time limit : 267 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for NoC3x3-PT-7B-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[*** LOG ERROR #0002 ***] [2024-05-30 19:50:41] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 70 (type EXCL) for 69 NoC3x3-PT-7B-LTLFireability-15
[[35mlola[0m][I] time limit : 385 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for NoC3x3-PT-7B-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 45
[[35mlola[0m][I] fired transitions : 45
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 NoC3x3-PT-7B-LTLFireability-02
[[35mlola[0m][I] time limit : 433 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 1/433 1/2000 NoC3x3-PT-7B-LTLFireability-02 24387 m, 4877 m/sec, 31242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 6/433 5/2000 NoC3x3-PT-7B-LTLFireability-02 221280 m, 39378 m/sec, 262187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 11/433 9/2000 NoC3x3-PT-7B-LTLFireability-02 405849 m, 36913 m/sec, 498442 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 16/433 13/2000 NoC3x3-PT-7B-LTLFireability-02 590248 m, 36879 m/sec, 739986 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 21/433 17/2000 NoC3x3-PT-7B-LTLFireability-02 771591 m, 36268 m/sec, 979999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 26/433 21/2000 NoC3x3-PT-7B-LTLFireability-02 958556 m, 37393 m/sec, 1219602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 31/433 25/2000 NoC3x3-PT-7B-LTLFireability-02 1142339 m, 36756 m/sec, 1462980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 36/433 29/2000 NoC3x3-PT-7B-LTLFireability-02 1332784 m, 38089 m/sec, 1698287 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 41/433 34/2000 NoC3x3-PT-7B-LTLFireability-02 1548028 m, 43048 m/sec, 1926829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 46/433 41/2000 NoC3x3-PT-7B-LTLFireability-02 1758881 m, 42170 m/sec, 2151922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 51/433 47/2000 NoC3x3-PT-7B-LTLFireability-02 1969500 m, 42123 m/sec, 2376705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 56/433 53/2000 NoC3x3-PT-7B-LTLFireability-02 2178731 m, 41846 m/sec, 2600064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 61/433 59/2000 NoC3x3-PT-7B-LTLFireability-02 2388631 m, 41980 m/sec, 2824147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 66/433 64/2000 NoC3x3-PT-7B-LTLFireability-02 2597616 m, 41797 m/sec, 3047253 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 71/433 70/2000 NoC3x3-PT-7B-LTLFireability-02 2806215 m, 41719 m/sec, 3269908 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 76/433 76/2000 NoC3x3-PT-7B-LTLFireability-02 3015228 m, 41802 m/sec, 3493028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 81/433 82/2000 NoC3x3-PT-7B-LTLFireability-02 3223978 m, 41750 m/sec, 3715789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 86/433 88/2000 NoC3x3-PT-7B-LTLFireability-02 3429884 m, 41181 m/sec, 3937998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 91/433 96/2000 NoC3x3-PT-7B-LTLFireability-02 3629744 m, 39972 m/sec, 4164019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 96/433 105/2000 NoC3x3-PT-7B-LTLFireability-02 3836094 m, 41270 m/sec, 4380416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 101/433 114/2000 NoC3x3-PT-7B-LTLFireability-02 4041367 m, 41054 m/sec, 4595652 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 106/433 122/2000 NoC3x3-PT-7B-LTLFireability-02 4231199 m, 37966 m/sec, 4807576 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 111/433 127/2000 NoC3x3-PT-7B-LTLFireability-02 4440611 m, 41882 m/sec, 5031276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 116/433 130/2000 NoC3x3-PT-7B-LTLFireability-02 4655854 m, 43048 m/sec, 5261779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 121/433 134/2000 NoC3x3-PT-7B-LTLFireability-02 4866072 m, 42043 m/sec, 5496605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 126/433 138/2000 NoC3x3-PT-7B-LTLFireability-02 5073654 m, 41516 m/sec, 5730074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 131/433 141/2000 NoC3x3-PT-7B-LTLFireability-02 5281531 m, 41575 m/sec, 5967064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 136/433 145/2000 NoC3x3-PT-7B-LTLFireability-02 5499803 m, 43654 m/sec, 6200772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 141/433 149/2000 NoC3x3-PT-7B-LTLFireability-02 5716054 m, 43250 m/sec, 6432657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 146/433 153/2000 NoC3x3-PT-7B-LTLFireability-02 5930593 m, 42907 m/sec, 6663068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 151/433 157/2000 NoC3x3-PT-7B-LTLFireability-02 6145115 m, 42904 m/sec, 6892802 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 156/433 161/2000 NoC3x3-PT-7B-LTLFireability-02 6359789 m, 42934 m/sec, 7123008 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 161/433 164/2000 NoC3x3-PT-7B-LTLFireability-02 6573966 m, 42835 m/sec, 7352708 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 166/433 168/2000 NoC3x3-PT-7B-LTLFireability-02 6789825 m, 43171 m/sec, 7583860 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 171/433 172/2000 NoC3x3-PT-7B-LTLFireability-02 7005659 m, 43166 m/sec, 7815297 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 176/433 176/2000 NoC3x3-PT-7B-LTLFireability-02 7221933 m, 43254 m/sec, 8047210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 181/433 180/2000 NoC3x3-PT-7B-LTLFireability-02 7437369 m, 43087 m/sec, 8278569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 186/433 184/2000 NoC3x3-PT-7B-LTLFireability-02 7653233 m, 43172 m/sec, 8509712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 191/433 188/2000 NoC3x3-PT-7B-LTLFireability-02 7869101 m, 43173 m/sec, 8741215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 196/433 191/2000 NoC3x3-PT-7B-LTLFireability-02 8080781 m, 42336 m/sec, 8971082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 201/433 194/2000 NoC3x3-PT-7B-LTLFireability-02 8283006 m, 40445 m/sec, 9198153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 206/433 197/2000 NoC3x3-PT-7B-LTLFireability-02 8476210 m, 38640 m/sec, 9415812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 211/433 201/2000 NoC3x3-PT-7B-LTLFireability-02 8669881 m, 38734 m/sec, 9633628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 216/433 204/2000 NoC3x3-PT-7B-LTLFireability-02 8868226 m, 39669 m/sec, 9859456 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 221/433 208/2000 NoC3x3-PT-7B-LTLFireability-02 9081846 m, 42724 m/sec, 10088241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 226/433 212/2000 NoC3x3-PT-7B-LTLFireability-02 9295052 m, 42641 m/sec, 10316879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 231/433 216/2000 NoC3x3-PT-7B-LTLFireability-02 9508029 m, 42595 m/sec, 10545627 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 236/433 220/2000 NoC3x3-PT-7B-LTLFireability-02 9721924 m, 42779 m/sec, 10774693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 241/433 223/2000 NoC3x3-PT-7B-LTLFireability-02 9935944 m, 42804 m/sec, 11004221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 246/433 227/2000 NoC3x3-PT-7B-LTLFireability-02 10138520 m, 40515 m/sec, 11221584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 251/433 230/2000 NoC3x3-PT-7B-LTLFireability-02 10339471 m, 40190 m/sec, 11436916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 256/433 234/2000 NoC3x3-PT-7B-LTLFireability-02 10540592 m, 40224 m/sec, 11652407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 261/433 238/2000 NoC3x3-PT-7B-LTLFireability-02 10741180 m, 40117 m/sec, 11867664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 266/433 241/2000 NoC3x3-PT-7B-LTLFireability-02 10942287 m, 40221 m/sec, 12083150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 271/433 245/2000 NoC3x3-PT-7B-LTLFireability-02 11142884 m, 40119 m/sec, 12298424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 276/433 248/2000 NoC3x3-PT-7B-LTLFireability-02 11343943 m, 40211 m/sec, 12513853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 281/433 252/2000 NoC3x3-PT-7B-LTLFireability-02 11544729 m, 40157 m/sec, 12729334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 286/433 255/2000 NoC3x3-PT-7B-LTLFireability-02 11746065 m, 40267 m/sec, 12944726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 291/433 259/2000 NoC3x3-PT-7B-LTLFireability-02 11946835 m, 40154 m/sec, 13160515 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 296/433 262/2000 NoC3x3-PT-7B-LTLFireability-02 12148622 m, 40357 m/sec, 13376391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 301/433 266/2000 NoC3x3-PT-7B-LTLFireability-02 12349679 m, 40211 m/sec, 13592478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 306/433 269/2000 NoC3x3-PT-7B-LTLFireability-02 12551464 m, 40357 m/sec, 13808353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 311/433 273/2000 NoC3x3-PT-7B-LTLFireability-02 12750322 m, 39771 m/sec, 14021785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 316/433 276/2000 NoC3x3-PT-7B-LTLFireability-02 12950214 m, 39978 m/sec, 14235981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 276
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 321/433 280/2000 NoC3x3-PT-7B-LTLFireability-02 13149903 m, 39937 m/sec, 14450286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 326/433 283/2000 NoC3x3-PT-7B-LTLFireability-02 13352932 m, 40605 m/sec, 14667792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 331/433 287/2000 NoC3x3-PT-7B-LTLFireability-02 13562316 m, 41876 m/sec, 14892420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 336/433 291/2000 NoC3x3-PT-7B-LTLFireability-02 13767213 m, 40979 m/sec, 15111902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 341/433 294/2000 NoC3x3-PT-7B-LTLFireability-02 13976347 m, 41826 m/sec, 15336575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 294
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 346/433 298/2000 NoC3x3-PT-7B-LTLFireability-02 14181606 m, 41051 m/sec, 15556152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 298
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 351/433 302/2000 NoC3x3-PT-7B-LTLFireability-02 14391939 m, 42066 m/sec, 15782084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 302
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 356/433 305/2000 NoC3x3-PT-7B-LTLFireability-02 14595320 m, 40676 m/sec, 15999978 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 361/433 309/2000 NoC3x3-PT-7B-LTLFireability-02 14804876 m, 41911 m/sec, 16224761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 491 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 366/433 313/2000 NoC3x3-PT-7B-LTLFireability-02 15007751 m, 40575 m/sec, 16442130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 496 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 371/433 316/2000 NoC3x3-PT-7B-LTLFireability-02 15217766 m, 42003 m/sec, 16667395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 501 secs. Pages in use: 316
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 376/433 320/2000 NoC3x3-PT-7B-LTLFireability-02 15420331 m, 40513 m/sec, 16884742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 506 secs. Pages in use: 320
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 381/433 324/2000 NoC3x3-PT-7B-LTLFireability-02 15622667 m, 40467 m/sec, 17101547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 511 secs. Pages in use: 324
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 386/433 327/2000 NoC3x3-PT-7B-LTLFireability-02 15827022 m, 40871 m/sec, 17329569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 516 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 391/433 331/2000 NoC3x3-PT-7B-LTLFireability-02 16030575 m, 40710 m/sec, 17558846 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 521 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 396/433 334/2000 NoC3x3-PT-7B-LTLFireability-02 16237256 m, 41336 m/sec, 17791134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 526 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 401/433 338/2000 NoC3x3-PT-7B-LTLFireability-02 16443550 m, 41258 m/sec, 18023228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 531 secs. Pages in use: 338
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 406/433 342/2000 NoC3x3-PT-7B-LTLFireability-02 16642785 m, 39847 m/sec, 18252929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 536 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 411/433 345/2000 NoC3x3-PT-7B-LTLFireability-02 16853682 m, 42179 m/sec, 18479140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 541 secs. Pages in use: 345
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 416/433 349/2000 NoC3x3-PT-7B-LTLFireability-02 17064825 m, 42228 m/sec, 18705277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 546 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 421/433 353/2000 NoC3x3-PT-7B-LTLFireability-02 17275084 m, 42051 m/sec, 18931127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 551 secs. Pages in use: 353
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 426/433 357/2000 NoC3x3-PT-7B-LTLFireability-02 17487582 m, 42499 m/sec, 19158708 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 556 secs. Pages in use: 357
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 431/433 360/2000 NoC3x3-PT-7B-LTLFireability-02 17697954 m, 42074 m/sec, 19384379 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 561 secs. Pages in use: 360
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for NoC3x3-PT-7B-LTLFireability-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 566 secs. Pages in use: 364
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 NoC3x3-PT-7B-LTLFireability-08
[[35mlola[0m][I] time limit : 433 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 NoC3x3-PT-7B-LTLFireability-02
[[35mlola[0m][I] time limit : 3034 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for NoC3x3-PT-7B-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 45
[[35mlola[0m][I] fired transitions : 45
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 5/433 5/5 NoC3x3-PT-7B-LTLFireability-02 194983 m, -3500594 m/sec, 224105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 571 secs. Pages in use: 369
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 7 (type EXCL) for NoC3x3-PT-7B-LTLFireability-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 576 secs. Pages in use: 369
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 NoC3x3-PT-7B-LTLFireability-07
[[35mlola[0m][I] time limit : 504 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for NoC3x3-PT-7B-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 22 NoC3x3-PT-7B-LTLFireability-06
[[35mlola[0m][I] time limit : 604 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 5/604 3/2000 NoC3x3-PT-7B-LTLFireability-06 178485 m, 35697 m/sec, 232929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 581 secs. Pages in use: 369
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 10/604 6/2000 NoC3x3-PT-7B-LTLFireability-06 362960 m, 36895 m/sec, 461542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 586 secs. Pages in use: 370
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 15/604 10/2000 NoC3x3-PT-7B-LTLFireability-06 560528 m, 39513 m/sec, 686496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 591 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 20/604 14/2000 NoC3x3-PT-7B-LTLFireability-06 759981 m, 39890 m/sec, 912198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 596 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 25/604 18/2000 NoC3x3-PT-7B-LTLFireability-06 947405 m, 37484 m/sec, 1138663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 601 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 30/604 21/2000 NoC3x3-PT-7B-LTLFireability-06 1129681 m, 36455 m/sec, 1364648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 606 secs. Pages in use: 385
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 35/604 24/2000 NoC3x3-PT-7B-LTLFireability-06 1313515 m, 36766 m/sec, 1589473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 611 secs. Pages in use: 388
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 40/604 27/2000 NoC3x3-PT-7B-LTLFireability-06 1492463 m, 35789 m/sec, 1811548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 616 secs. Pages in use: 391
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 45/604 29/2000 NoC3x3-PT-7B-LTLFireability-06 1673185 m, 36144 m/sec, 2034904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 621 secs. Pages in use: 393
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 50/604 32/2000 NoC3x3-PT-7B-LTLFireability-06 1861288 m, 37620 m/sec, 2257655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 626 secs. Pages in use: 396
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 55/604 35/2000 NoC3x3-PT-7B-LTLFireability-06 2052267 m, 38195 m/sec, 2477082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages in use: 399
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 60/604 38/2000 NoC3x3-PT-7B-LTLFireability-06 2244293 m, 38405 m/sec, 2697416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 636 secs. Pages in use: 402
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 65/604 40/2000 NoC3x3-PT-7B-LTLFireability-06 2416500 m, 34441 m/sec, 2924760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 641 secs. Pages in use: 404
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 70/604 43/2000 NoC3x3-PT-7B-LTLFireability-06 2597277 m, 36155 m/sec, 3159057 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 646 secs. Pages in use: 407
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 75/604 45/2000 NoC3x3-PT-7B-LTLFireability-06 2778990 m, 36342 m/sec, 3392661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 651 secs. Pages in use: 409
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 80/604 49/2000 NoC3x3-PT-7B-LTLFireability-06 2973983 m, 38998 m/sec, 3621676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 656 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 85/604 51/2000 NoC3x3-PT-7B-LTLFireability-06 3143521 m, 33907 m/sec, 3855549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 661 secs. Pages in use: 415
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 90/604 53/2000 NoC3x3-PT-7B-LTLFireability-06 3308531 m, 33002 m/sec, 4089452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 666 secs. Pages in use: 417
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 95/604 56/2000 NoC3x3-PT-7B-LTLFireability-06 3487275 m, 35748 m/sec, 4320676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 671 secs. Pages in use: 420
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 100/604 59/2000 NoC3x3-PT-7B-LTLFireability-06 3669571 m, 36459 m/sec, 4552223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 676 secs. Pages in use: 423
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 105/604 62/2000 NoC3x3-PT-7B-LTLFireability-06 3847997 m, 35685 m/sec, 4784732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 681 secs. Pages in use: 426
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 110/604 65/2000 NoC3x3-PT-7B-LTLFireability-06 4033776 m, 37155 m/sec, 5015090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 686 secs. Pages in use: 429
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 115/604 68/2000 NoC3x3-PT-7B-LTLFireability-06 4225754 m, 38395 m/sec, 5243319 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 691 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 120/604 70/2000 NoC3x3-PT-7B-LTLFireability-06 4389920 m, 32833 m/sec, 5476312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 696 secs. Pages in use: 434
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 125/604 72/2000 NoC3x3-PT-7B-LTLFireability-06 4557635 m, 33543 m/sec, 5710192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 701 secs. Pages in use: 436
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 130/604 75/2000 NoC3x3-PT-7B-LTLFireability-06 4737537 m, 35980 m/sec, 5941820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 706 secs. Pages in use: 439
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 135/604 77/2000 NoC3x3-PT-7B-LTLFireability-06 4901049 m, 32702 m/sec, 6174610 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 711 secs. Pages in use: 441
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 140/604 80/2000 NoC3x3-PT-7B-LTLFireability-06 5065329 m, 32856 m/sec, 6407740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 716 secs. Pages in use: 444
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 145/604 83/2000 NoC3x3-PT-7B-LTLFireability-06 5243300 m, 35594 m/sec, 6638149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 721 secs. Pages in use: 447
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 150/604 85/2000 NoC3x3-PT-7B-LTLFireability-06 5413015 m, 33943 m/sec, 6870180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 726 secs. Pages in use: 449
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 155/604 87/2000 NoC3x3-PT-7B-LTLFireability-06 5577180 m, 32833 m/sec, 7104415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 731 secs. Pages in use: 451
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 160/604 90/2000 NoC3x3-PT-7B-LTLFireability-06 5751945 m, 34953 m/sec, 7337037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 736 secs. Pages in use: 454
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 165/604 93/2000 NoC3x3-PT-7B-LTLFireability-06 5925136 m, 34638 m/sec, 7569818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 741 secs. Pages in use: 457
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 170/604 95/2000 NoC3x3-PT-7B-LTLFireability-06 6089830 m, 32938 m/sec, 7803790 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 746 secs. Pages in use: 459
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 175/604 97/2000 NoC3x3-PT-7B-LTLFireability-06 6262330 m, 34500 m/sec, 8036925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 751 secs. Pages in use: 461
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 180/604 100/2000 NoC3x3-PT-7B-LTLFireability-06 6437494 m, 35032 m/sec, 8269005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 756 secs. Pages in use: 464
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 185/604 102/2000 NoC3x3-PT-7B-LTLFireability-06 6601476 m, 32796 m/sec, 8502857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 761 secs. Pages in use: 466
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 190/604 105/2000 NoC3x3-PT-7B-LTLFireability-06 6770120 m, 33728 m/sec, 8736533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 766 secs. Pages in use: 469
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 195/604 108/2000 NoC3x3-PT-7B-LTLFireability-06 6949899 m, 35955 m/sec, 8968197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 771 secs. Pages in use: 472
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 200/604 110/2000 NoC3x3-PT-7B-LTLFireability-06 7113487 m, 32717 m/sec, 9201635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 776 secs. Pages in use: 474
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 205/604 112/2000 NoC3x3-PT-7B-LTLFireability-06 7278912 m, 33085 m/sec, 9435864 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 781 secs. Pages in use: 476
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 210/604 115/2000 NoC3x3-PT-7B-LTLFireability-06 7458062 m, 35830 m/sec, 9667403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 786 secs. Pages in use: 479
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 215/604 117/2000 NoC3x3-PT-7B-LTLFireability-06 7626675 m, 33722 m/sec, 9901046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 791 secs. Pages in use: 481
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 220/604 120/2000 NoC3x3-PT-7B-LTLFireability-06 7791327 m, 32930 m/sec, 10135190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 796 secs. Pages in use: 484
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 225/604 122/2000 NoC3x3-PT-7B-LTLFireability-06 7969429 m, 35620 m/sec, 10367088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 801 secs. Pages in use: 486
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 230/604 125/2000 NoC3x3-PT-7B-LTLFireability-06 8138845 m, 33883 m/sec, 10600196 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 806 secs. Pages in use: 489
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 235/604 127/2000 NoC3x3-PT-7B-LTLFireability-06 8303287 m, 32888 m/sec, 10834638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 811 secs. Pages in use: 491
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 240/604 130/2000 NoC3x3-PT-7B-LTLFireability-06 8477816 m, 34905 m/sec, 11067168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 816 secs. Pages in use: 494
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 245/604 132/2000 NoC3x3-PT-7B-LTLFireability-06 8650325 m, 34501 m/sec, 11298984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 821 secs. Pages in use: 496
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 250/604 135/2000 NoC3x3-PT-7B-LTLFireability-06 8813884 m, 32711 m/sec, 11531788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 826 secs. Pages in use: 499
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 255/604 137/2000 NoC3x3-PT-7B-LTLFireability-06 8983613 m, 33945 m/sec, 11764085 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 831 secs. Pages in use: 501
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 260/604 140/2000 NoC3x3-PT-7B-LTLFireability-06 9162484 m, 35774 m/sec, 11994825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 836 secs. Pages in use: 504
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 265/604 142/2000 NoC3x3-PT-7B-LTLFireability-06 9325935 m, 32690 m/sec, 12228936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 841 secs. Pages in use: 506
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 270/604 144/2000 NoC3x3-PT-7B-LTLFireability-06 9493616 m, 33536 m/sec, 12463012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 846 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 275/604 147/2000 NoC3x3-PT-7B-LTLFireability-06 9673510 m, 35978 m/sec, 12694629 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 851 secs. Pages in use: 511
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 280/604 150/2000 NoC3x3-PT-7B-LTLFireability-06 9837560 m, 32810 m/sec, 12928112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 856 secs. Pages in use: 514
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 285/604 152/2000 NoC3x3-PT-7B-LTLFireability-06 10003264 m, 33140 m/sec, 13162372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 861 secs. Pages in use: 516
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 290/604 155/2000 NoC3x3-PT-7B-LTLFireability-06 10181033 m, 35553 m/sec, 13393630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 866 secs. Pages in use: 519
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 295/604 157/2000 NoC3x3-PT-7B-LTLFireability-06 10349638 m, 33721 m/sec, 13626956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 871 secs. Pages in use: 521
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 300/604 159/2000 NoC3x3-PT-7B-LTLFireability-06 10513978 m, 32868 m/sec, 13861417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 876 secs. Pages in use: 523
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 305/604 162/2000 NoC3x3-PT-7B-LTLFireability-06 10690889 m, 35382 m/sec, 14093805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 881 secs. Pages in use: 526
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 310/604 165/2000 NoC3x3-PT-7B-LTLFireability-06 10863456 m, 34513 m/sec, 14326642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 886 secs. Pages in use: 529
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 315/604 167/2000 NoC3x3-PT-7B-LTLFireability-06 11027699 m, 32848 m/sec, 14560627 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 891 secs. Pages in use: 531
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 320/604 170/2000 NoC3x3-PT-7B-LTLFireability-06 11200698 m, 34599 m/sec, 14793397 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 896 secs. Pages in use: 534
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 325/604 172/2000 NoC3x3-PT-7B-LTLFireability-06 11375344 m, 34929 m/sec, 15025408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 901 secs. Pages in use: 536
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 330/604 175/2000 NoC3x3-PT-7B-LTLFireability-06 11543529 m, 33637 m/sec, 15257856 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 906 secs. Pages in use: 539
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 335/604 177/2000 NoC3x3-PT-7B-LTLFireability-06 11713572 m, 34008 m/sec, 15490380 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 911 secs. Pages in use: 541
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 340/604 180/2000 NoC3x3-PT-7B-LTLFireability-06 11895943 m, 36474 m/sec, 15720581 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 916 secs. Pages in use: 544
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 345/604 183/2000 NoC3x3-PT-7B-LTLFireability-06 12063829 m, 33577 m/sec, 15953284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 921 secs. Pages in use: 547
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 350/604 185/2000 NoC3x3-PT-7B-LTLFireability-06 12227766 m, 32787 m/sec, 16187796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 926 secs. Pages in use: 549
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 355/604 188/2000 NoC3x3-PT-7B-LTLFireability-06 12406558 m, 35758 m/sec, 16419168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 931 secs. Pages in use: 552
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 360/604 191/2000 NoC3x3-PT-7B-LTLFireability-06 12591701 m, 37028 m/sec, 16649717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 936 secs. Pages in use: 555
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 365/604 193/2000 NoC3x3-PT-7B-LTLFireability-06 12774840 m, 36627 m/sec, 16880064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 941 secs. Pages in use: 557
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 370/604 196/2000 NoC3x3-PT-7B-LTLFireability-06 12953169 m, 35665 m/sec, 17110774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 946 secs. Pages in use: 560
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 375/604 199/2000 NoC3x3-PT-7B-LTLFireability-06 13143139 m, 37994 m/sec, 17337952 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 951 secs. Pages in use: 563
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 380/604 202/2000 NoC3x3-PT-7B-LTLFireability-06 13333307 m, 38033 m/sec, 17566567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 956 secs. Pages in use: 566
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 385/604 206/2000 NoC3x3-PT-7B-LTLFireability-06 13527249 m, 38788 m/sec, 17794396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 961 secs. Pages in use: 570
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 390/604 209/2000 NoC3x3-PT-7B-LTLFireability-06 13709797 m, 36509 m/sec, 18025173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 966 secs. Pages in use: 573
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 395/604 211/2000 NoC3x3-PT-7B-LTLFireability-06 13874338 m, 32908 m/sec, 18260707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 971 secs. Pages in use: 575
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 400/604 213/2000 NoC3x3-PT-7B-LTLFireability-06 14047565 m, 34645 m/sec, 18493601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 976 secs. Pages in use: 577
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 405/604 216/2000 NoC3x3-PT-7B-LTLFireability-06 14217977 m, 34082 m/sec, 18726091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 981 secs. Pages in use: 580
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 410/604 219/2000 NoC3x3-PT-7B-LTLFireability-06 14396498 m, 35704 m/sec, 18956853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 986 secs. Pages in use: 583
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 415/604 222/2000 NoC3x3-PT-7B-LTLFireability-06 14576548 m, 36010 m/sec, 19187288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 991 secs. Pages in use: 586
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 420/604 225/2000 NoC3x3-PT-7B-LTLFireability-06 14767526 m, 38195 m/sec, 19413339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 996 secs. Pages in use: 589
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 425/604 228/2000 NoC3x3-PT-7B-LTLFireability-06 14961100 m, 38714 m/sec, 19640129 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1001 secs. Pages in use: 592
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 430/604 231/2000 NoC3x3-PT-7B-LTLFireability-06 15140678 m, 35915 m/sec, 19870853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1006 secs. Pages in use: 595
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 435/604 234/2000 NoC3x3-PT-7B-LTLFireability-06 15320155 m, 35895 m/sec, 20101165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1011 secs. Pages in use: 598
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 440/604 237/2000 NoC3x3-PT-7B-LTLFireability-06 15497373 m, 35443 m/sec, 20330551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1016 secs. Pages in use: 601
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 445/604 240/2000 NoC3x3-PT-7B-LTLFireability-06 15676274 m, 35780 m/sec, 20560681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1021 secs. Pages in use: 604
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 450/604 243/2000 NoC3x3-PT-7B-LTLFireability-06 15853060 m, 35357 m/sec, 20790597 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1026 secs. Pages in use: 607
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 455/604 246/2000 NoC3x3-PT-7B-LTLFireability-06 16032236 m, 35835 m/sec, 21021410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1031 secs. Pages in use: 610
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 460/604 249/2000 NoC3x3-PT-7B-LTLFireability-06 16231403 m, 39833 m/sec, 21246829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1036 secs. Pages in use: 613
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 465/604 254/2000 NoC3x3-PT-7B-LTLFireability-06 16431552 m, 40029 m/sec, 21469974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1041 secs. Pages in use: 618
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 470/604 258/2000 NoC3x3-PT-7B-LTLFireability-06 16631260 m, 39941 m/sec, 21693558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1046 secs. Pages in use: 622
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 475/604 262/2000 NoC3x3-PT-7B-LTLFireability-06 16831210 m, 39990 m/sec, 21917255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1051 secs. Pages in use: 626
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 480/604 266/2000 NoC3x3-PT-7B-LTLFireability-06 17030272 m, 39812 m/sec, 22139984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1056 secs. Pages in use: 630
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 485/604 270/2000 NoC3x3-PT-7B-LTLFireability-06 17216275 m, 37200 m/sec, 22362546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1061 secs. Pages in use: 634
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 490/604 273/2000 NoC3x3-PT-7B-LTLFireability-06 17403735 m, 37492 m/sec, 22586582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1066 secs. Pages in use: 637
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 495/604 277/2000 NoC3x3-PT-7B-LTLFireability-06 17592164 m, 37685 m/sec, 22811391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1071 secs. Pages in use: 641
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 500/604 281/2000 NoC3x3-PT-7B-LTLFireability-06 17784860 m, 38539 m/sec, 23034946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1076 secs. Pages in use: 645
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 505/604 285/2000 NoC3x3-PT-7B-LTLFireability-06 17972552 m, 37538 m/sec, 23257196 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1081 secs. Pages in use: 649
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 510/604 289/2000 NoC3x3-PT-7B-LTLFireability-06 18161294 m, 37748 m/sec, 23480312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1086 secs. Pages in use: 653
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 515/604 293/2000 NoC3x3-PT-7B-LTLFireability-06 18350388 m, 37818 m/sec, 23703997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1091 secs. Pages in use: 657
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 520/604 297/2000 NoC3x3-PT-7B-LTLFireability-06 18543870 m, 38696 m/sec, 23926463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1096 secs. Pages in use: 661
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 525/604 300/2000 NoC3x3-PT-7B-LTLFireability-06 18730432 m, 37312 m/sec, 24149104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1101 secs. Pages in use: 664
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 530/604 304/2000 NoC3x3-PT-7B-LTLFireability-06 18917829 m, 37479 m/sec, 24372803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1106 secs. Pages in use: 668
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 535/604 308/2000 NoC3x3-PT-7B-LTLFireability-06 19105554 m, 37545 m/sec, 24596994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1111 secs. Pages in use: 672
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 540/604 312/2000 NoC3x3-PT-7B-LTLFireability-06 19298120 m, 38513 m/sec, 24820737 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1116 secs. Pages in use: 676
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 545/604 315/2000 NoC3x3-PT-7B-LTLFireability-06 19486642 m, 37704 m/sec, 25043715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1121 secs. Pages in use: 679
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 550/604 319/2000 NoC3x3-PT-7B-LTLFireability-06 19675429 m, 37757 m/sec, 25266937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1126 secs. Pages in use: 683
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 555/604 323/2000 NoC3x3-PT-7B-LTLFireability-06 19864632 m, 37840 m/sec, 25490414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1131 secs. Pages in use: 687
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 560/604 327/2000 NoC3x3-PT-7B-LTLFireability-06 20057432 m, 38560 m/sec, 25713976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1136 secs. Pages in use: 691
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 565/604 331/2000 NoC3x3-PT-7B-LTLFireability-06 20247669 m, 38047 m/sec, 25938573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1141 secs. Pages in use: 695
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 570/604 335/2000 NoC3x3-PT-7B-LTLFireability-06 20436405 m, 37747 m/sec, 26164030 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1146 secs. Pages in use: 699
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 575/604 339/2000 NoC3x3-PT-7B-LTLFireability-06 20625663 m, 37851 m/sec, 26390060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1151 secs. Pages in use: 703
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 580/604 343/2000 NoC3x3-PT-7B-LTLFireability-06 20818333 m, 38534 m/sec, 26615545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1156 secs. Pages in use: 707
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 585/604 346/2000 NoC3x3-PT-7B-LTLFireability-06 21007938 m, 37921 m/sec, 26840016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1161 secs. Pages in use: 710
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 590/604 350/2000 NoC3x3-PT-7B-LTLFireability-06 21194864 m, 37385 m/sec, 27063367 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1166 secs. Pages in use: 714
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 595/604 354/2000 NoC3x3-PT-7B-LTLFireability-06 21382792 m, 37585 m/sec, 27287823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1171 secs. Pages in use: 718
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 LTL EXCL 600/604 358/2000 NoC3x3-PT-7B-LTLFireability-06 21574417 m, 38325 m/sec, 27512049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1176 secs. Pages in use: 722
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 27 (type EXCL) for NoC3x3-PT-7B-LTLFireability-06 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 1 0 0 2 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1181 secs. Pages in use: 726
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 22 NoC3x3-PT-7B-LTLFireability-06
[[35mlola[0m][I] time limit : 604 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 22 NoC3x3-PT-7B-LTLFireability-06
[[35mlola[0m][I] time limit : 2419 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 2 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 5/604 4/2000 NoC3x3-PT-7B-LTLFireability-06 194949 m, 38989 m/sec, 219975 t fired, .
[[35mlola[0m][.] 27 LTL EXCL 5/2419 3/5 NoC3x3-PT-7B-LTLFireability-06 171015 m, -4280680 m/sec, 223137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1186 secs. Pages in use: 733
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 27 (type EXCL) for NoC3x3-PT-7B-LTLFireability-06 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 10/604 6/2000 NoC3x3-PT-7B-LTLFireability-06 385876 m, 38185 m/sec, 442306 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1191 secs. Pages in use: 737
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 15/604 8/2000 NoC3x3-PT-7B-LTLFireability-06 564458 m, 35716 m/sec, 682418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1196 secs. Pages in use: 737
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 20/604 11/2000 NoC3x3-PT-7B-LTLFireability-06 750672 m, 37242 m/sec, 918676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1201 secs. Pages in use: 737
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 25/604 14/2000 NoC3x3-PT-7B-LTLFireability-06 935300 m, 36925 m/sec, 1154961 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1206 secs. Pages in use: 740
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 30/604 16/2000 NoC3x3-PT-7B-LTLFireability-06 1111270 m, 35194 m/sec, 1394034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1211 secs. Pages in use: 742
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 35/604 19/2000 NoC3x3-PT-7B-LTLFireability-06 1295201 m, 36786 m/sec, 1630186 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1216 secs. Pages in use: 745
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 40/604 21/2000 NoC3x3-PT-7B-LTLFireability-06 1479723 m, 36904 m/sec, 1866584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1221 secs. Pages in use: 747
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 45/604 23/2000 NoC3x3-PT-7B-LTLFireability-06 1654767 m, 35008 m/sec, 2105620 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1226 secs. Pages in use: 749
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 50/604 26/2000 NoC3x3-PT-7B-LTLFireability-06 1839275 m, 36901 m/sec, 2342175 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1231 secs. Pages in use: 752
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 55/604 29/2000 NoC3x3-PT-7B-LTLFireability-06 2024122 m, 36969 m/sec, 2578501 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1236 secs. Pages in use: 755
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 60/604 31/2000 NoC3x3-PT-7B-LTLFireability-06 2199969 m, 35169 m/sec, 2817374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1241 secs. Pages in use: 757
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 65/604 34/2000 NoC3x3-PT-7B-LTLFireability-06 2389429 m, 37892 m/sec, 3052109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1246 secs. Pages in use: 760
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 70/604 36/2000 NoC3x3-PT-7B-LTLFireability-06 2581043 m, 38322 m/sec, 3286397 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1251 secs. Pages in use: 762
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 75/604 39/2000 NoC3x3-PT-7B-LTLFireability-06 2777679 m, 39327 m/sec, 3517935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1256 secs. Pages in use: 765
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 80/604 43/2000 NoC3x3-PT-7B-LTLFireability-06 2991938 m, 42851 m/sec, 3743676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1261 secs. Pages in use: 769
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 85/604 46/2000 NoC3x3-PT-7B-LTLFireability-06 3202876 m, 42187 m/sec, 3967691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1266 secs. Pages in use: 772
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 90/604 50/2000 NoC3x3-PT-7B-LTLFireability-06 3410757 m, 41576 m/sec, 4189650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1271 secs. Pages in use: 776
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 95/604 54/2000 NoC3x3-PT-7B-LTLFireability-06 3620074 m, 41863 m/sec, 4413070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1276 secs. Pages in use: 780
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 100/604 58/2000 NoC3x3-PT-7B-LTLFireability-06 3829562 m, 41897 m/sec, 4636700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1281 secs. Pages in use: 784
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 105/604 61/2000 NoC3x3-PT-7B-LTLFireability-06 4038432 m, 41774 m/sec, 4859596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1286 secs. Pages in use: 787
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 110/604 65/2000 NoC3x3-PT-7B-LTLFireability-06 4246380 m, 41589 m/sec, 5081512 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1291 secs. Pages in use: 791
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 115/604 68/2000 NoC3x3-PT-7B-LTLFireability-06 4453570 m, 41438 m/sec, 5302741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1296 secs. Pages in use: 794
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 120/604 72/2000 NoC3x3-PT-7B-LTLFireability-06 4661182 m, 41522 m/sec, 5524388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1301 secs. Pages in use: 798
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 125/604 76/2000 NoC3x3-PT-7B-LTLFireability-06 4869281 m, 41619 m/sec, 5746440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1306 secs. Pages in use: 802
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 130/604 79/2000 NoC3x3-PT-7B-LTLFireability-06 5077005 m, 41544 m/sec, 5968221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1311 secs. Pages in use: 805
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 135/604 83/2000 NoC3x3-PT-7B-LTLFireability-06 5284782 m, 41555 m/sec, 6190042 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1316 secs. Pages in use: 809
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 140/604 86/2000 NoC3x3-PT-7B-LTLFireability-06 5492262 m, 41496 m/sec, 6411444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1321 secs. Pages in use: 812
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 145/604 90/2000 NoC3x3-PT-7B-LTLFireability-06 5699109 m, 41369 m/sec, 6632317 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1326 secs. Pages in use: 816
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 150/604 94/2000 NoC3x3-PT-7B-LTLFireability-06 5905411 m, 41260 m/sec, 6852491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1331 secs. Pages in use: 820
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 155/604 97/2000 NoC3x3-PT-7B-LTLFireability-06 6112645 m, 41446 m/sec, 7073742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1336 secs. Pages in use: 823
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 160/604 101/2000 NoC3x3-PT-7B-LTLFireability-06 6319889 m, 41448 m/sec, 7294963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1341 secs. Pages in use: 827
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 165/604 105/2000 NoC3x3-PT-7B-LTLFireability-06 6526998 m, 41421 m/sec, 7515980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1346 secs. Pages in use: 831
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 170/604 108/2000 NoC3x3-PT-7B-LTLFireability-06 6732836 m, 41167 m/sec, 7735730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1351 secs. Pages in use: 834
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 175/604 112/2000 NoC3x3-PT-7B-LTLFireability-06 6926861 m, 38805 m/sec, 7959883 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1356 secs. Pages in use: 838
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 180/604 116/2000 NoC3x3-PT-7B-LTLFireability-06 7123350 m, 39297 m/sec, 8185238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1361 secs. Pages in use: 842
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 185/604 121/2000 NoC3x3-PT-7B-LTLFireability-06 7334293 m, 42188 m/sec, 8406475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1366 secs. Pages in use: 847
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 190/604 126/2000 NoC3x3-PT-7B-LTLFireability-06 7542850 m, 41711 m/sec, 8625178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1371 secs. Pages in use: 852
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 195/604 132/2000 NoC3x3-PT-7B-LTLFireability-06 7751389 m, 41707 m/sec, 8843897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1376 secs. Pages in use: 858
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 200/604 137/2000 NoC3x3-PT-7B-LTLFireability-06 7959322 m, 41586 m/sec, 9061954 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1381 secs. Pages in use: 863
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 205/604 142/2000 NoC3x3-PT-7B-LTLFireability-06 8167244 m, 41584 m/sec, 9279993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1386 secs. Pages in use: 868
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 210/604 147/2000 NoC3x3-PT-7B-LTLFireability-06 8354412 m, 37433 m/sec, 9500361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1391 secs. Pages in use: 873
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 215/604 152/2000 NoC3x3-PT-7B-LTLFireability-06 8554766 m, 40070 m/sec, 9712014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1396 secs. Pages in use: 878
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 220/604 154/2000 NoC3x3-PT-7B-LTLFireability-06 8765253 m, 42097 m/sec, 9938099 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1401 secs. Pages in use: 880
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 225/604 156/2000 NoC3x3-PT-7B-LTLFireability-06 8977780 m, 42505 m/sec, 10165714 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1406 secs. Pages in use: 882
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 230/604 159/2000 NoC3x3-PT-7B-LTLFireability-06 9190967 m, 42637 m/sec, 10394676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1411 secs. Pages in use: 885
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 235/604 162/2000 NoC3x3-PT-7B-LTLFireability-06 9403310 m, 42468 m/sec, 10622675 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1416 secs. Pages in use: 888
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 240/604 164/2000 NoC3x3-PT-7B-LTLFireability-06 9607882 m, 40914 m/sec, 10852616 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1421 secs. Pages in use: 890
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 245/604 166/2000 NoC3x3-PT-7B-LTLFireability-06 9812519 m, 40927 m/sec, 11083803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1426 secs. Pages in use: 892
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 250/604 169/2000 NoC3x3-PT-7B-LTLFireability-06 10019040 m, 41304 m/sec, 11315241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1431 secs. Pages in use: 895
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 255/604 171/2000 NoC3x3-PT-7B-LTLFireability-06 10224068 m, 41005 m/sec, 11546896 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1436 secs. Pages in use: 897
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 260/604 174/2000 NoC3x3-PT-7B-LTLFireability-06 10420368 m, 39260 m/sec, 11781312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1441 secs. Pages in use: 900
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 265/604 176/2000 NoC3x3-PT-7B-LTLFireability-06 10634022 m, 42730 m/sec, 12009474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1446 secs. Pages in use: 902
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-05: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-09: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-10: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-12: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-7B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-7B-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-7B-LTLFireability-06: CONJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 270/604 179/2000 NoC3x3-PT-7B-LTLFireability-06 10839120 m, 41019 m/sec, 12229861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1451 secs. Pages in use: 905
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 395 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="NoC3x3-PT-7B"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is NoC3x3-PT-7B, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654353800660"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/NoC3x3-PT-7B.tgz
mv NoC3x3-PT-7B execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;